ASIC Design Exploration for DSP and FEC of 400-Gbit/s Coherent Data-Center Interconnect Receivers
Paper in proceedings, 2020

We perform exploratory ASIC design of key DSP and FEC units for 400-Gbit/s coherent data-center interconnect receivers. In 22-nm CMOS, the considered units together dissipate 5W, suggesting implementation feasibility in power-constrained form factors.

Author

Christoffer Fougstedt

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers), Electronics Systems

Oscar Gustafsson

Linköping University

Cheolyong Bae

Linköping University

Erik Börjeson

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers), Electronics Systems

Per Larsson-Edefors

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers), Electronics Systems

2020 Optical Fiber Communications Conference and Exhibition, OFC 2020 - Proceedings

9083075

Optical Fiber Communication Conference, OFC 2020
San Diego, USA,

Energy-efficient optical fibre communication

Knut and Alice Wallenberg Foundation, 2014-07-01 -- 2019-06-30.

Energieffektiv och höghastighets-transmission i optisk fiber kommunikation

VINNOVA, 2018-01-01 -- 2019-12-31.

Areas of Advance

Information and Communication Technology

Subject Categories

Communication Systems

Embedded Systems

Signal Processing

DOI

10.1364/OFC.2020.Th2A.38

ISBN

9781943580712

More information

Latest update

12/29/2020