Low-Power Low-Latency BCH Decoders for Energy-Efficient Optical Interconnects
Journal article, 2017

Since energy dissipation and latency in optical interconnects are of utmost concern, such links are often operated without forward error correction. We propose a low-complexity non-iterative 2-error correcting BCH decoder circuit that significantly relaxes the stringent optical modulation amplitude requirements on the transmitter, which help to reduce laser and laser driver energy. We demonstrate, in a 28-nm CMOS process technology, that the introduction of this BCH circuit in an uncoded link leads to energy-per-bit reductions of 25%, even when impact of code rate on receiver energy dissipation is considered.

Author

Christoffer Fougstedt

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Krzysztof Szczerba

Chalmers, Microtechnology and Nanoscience (MC2), Photonics

Per Larsson-Edefors

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Journal of Lightwave Technology

0733-8724 (ISSN)

Vol. 35 23 5201-5207

Areas of Advance

Information and Communication Technology

Subject Categories

Communication Systems

Other Electrical Engineering, Electronic Engineering, Information Engineering

DOI

10.1109/JLT.2017.2764679

More information

Latest update

4/20/2018