Fault Simulation and Physical Fault Injection Applied to MOS Transistor Networks
Detailed information on a system's behavior in the presence of faults is often vital. It may be used to grade or construct tests for the efficient detection of faults or to increase confidence in high-reliable systems. Fault injection, which is the process of artificially inserting faults into circuits, is in many cases the only feasible technique to obtain knowledge of the circuit in the presence of faults.
When realistic faults are introduced in switch-level descriptions of CMOS networks, steady-state undetermined node values (X) frequently occur in the networks, which reduces confidence in the simulation results. Two new algorithms to reduce the number of nodes assigned the undermined logic state are presented in this thesis. It is verified that the proposed algorithms increase the fault modeling capability of a switch-level simulator.
A switch-level fault simulation algorithm for the simulation of voltage transients in CMOS networks is also presented in the thesis. Electrical-level fault simulation can provide detailed information of the behavior of vital parts of a complex circuit in the presence of realistic faults. The thesis investigates the effects of node stuck-at and gate stuck-at faults in CMOS checkers. Furthermore, an investigation of a variety of transistor terminal short and open faults injected into CMOS checkers shows that the fault models can be reduced to four sets, for which the fault models included in each set show identical behavior.
It is possible to inject transients into a circuit by irradiating the circuit with heavy ions emitted from a Californium-252 source. The thesis presents a new experimental method based on heavy-ion radiation to determine to what extent particle-induced transients in combinational parts of a circuit propagate into memory elements. The thesis also presents a comparison between a Cf-252 fault injection experiment with the MC6809E microprocessor and an error injection experiment using a high level software simulation model of the processor.