Visible Bisimulation Equivalence - A Unified Abstraction for Temporal Logic Verification
Paper i proceeding, 2018

Bisimulation is an abstraction method that can be used to reduce the number of states for
transition systems. This paper presents an alternative formulation of bisimulation, directly based on an
equivalence relation and partitioning of the state space. The formulation, here called visible bisimulation
equivalence, unifies stuttering and branching bisimulation by including both state and event labels in
the abstraction. The proposed divergence-sensitive visible (DSV) bisimulation equivalence is shown to
be equivalent to a temporal logic called ECTL, where CTL is extended with events. This means that
DSV bisimulation equivalence preserves most temporal temporal logic properties that are of interest.
The proposed bisimulation abstraction is applied to a set of synchronized submodels, where local
events are identified incrementally and abstracted after each synchronization. Since the bisimulation
reduction is applied after each synchronization, a significant part of the state space explosion in ordinary
synchronization is avoided. Since the abstraction is polynomial in the number of states and transitions,
this is an attractive method for verification and synthesis based on temporal logic.

temporal logic verification

bisimulation

transition systems

abstraction

modular systems

Författare

Bengt Lennartson

Chalmers, Elektroteknik, System- och reglerteknik

Mona Noori-Hosseini

Chalmers, Elektroteknik, System- och reglerteknik, Automation

IFAC-PapersOnLine

2405-8963 (ISSN)

Vol. 51 7 400-407

14th Workshop on Discrete Event Systems (WODES'18)
Sorrento Coast, Italy,

Ämneskategorier

Algebra och logik

Inbäddad systemteknik

Diskret matematik

DOI

10.1016/j.ifacol.2018.06.332

Mer information

Senast uppdaterat

2018-09-11