VLSI Design of a 3-bit Constant-Modulus Precoder for Massive MU-MIMO
Paper i proceeding, 2018

Fifth-generation (5G) cellular systems will build on massive multi-user (MU) multiple-input multiple-output (MIMO) technology to attain high spectral efficiency. However, having hundreds of antennas and radio-frequency (RF) chains at the base station (BS) entails prohibitively high hardware costs and power consumption. This paper proposes a novel nonlinear precoding algorithm for the massive MU-MIMO downlink in which each RF chain contains an 8-phase (3-bit) constantmodulus transmitter, enabling the use of low-cost and powerefficient analog hardware. We present a high-throughput VLSI architecture and show implementation results on a Xilinx Virtex-7 FPGA. Compared to a recently-reported nonlinear precoder for BS designs that use two 1 -bit digital-to-analog converters per RF chain, our design enables up to 3:75 dB transmit power reduction at no more than a 2.7x increase in FPGA resources.

Författare

Oscar Castaneda

Cornell University

Sven Jacobsson

Chalmers, Elektroteknik, Kommunikations- och antennsystem, Kommunikationssystem

Giuseppe Durisi

Ericsson, Göteborg

Tom Goldstein

University of Maryland

Christoph Studer

Cornell University

2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)

0271-4302 (ISSN)

Ämneskategorier

Telekommunikation

Kommunikationssystem

Signalbehandling

DOI

10.1109/ISCAS.2018.8351894

ISBN

9781538648810

Mer information

Senast uppdaterat

2019-01-22