Hardware considerations for selection networks
Paper i proceeding, 2019

The selection operation is a central part of a soft-decision error-correction algorithm, which is important for high-performance communication networks. High symbol rates and power-dissipation limitations motivate hardware implementation as a comparator network. We use industry-standard tools to investigate VLSI hardware implementation of selection networks with up to 512 inputs. We find theoretical network depth and size to be poor predictors of hardware performance. In a 65-nm process, we find that our novel half-life network is competitive with and in some cases superior to Zazon-Ivry’s pairwise and odd/even selection networks, for delay, area, and energy per selection operation.

Författare

Kenneth Peter

Chalmers

Lars Svensson

Chalmers, Data- och informationsteknik, Datorteknik, Electronics Systems

Christoffer Fougstedt

Chalmers, Data- och informationsteknik, Datorteknik, Electronics Systems

Per Larsson-Edefors

Chalmers, Data- och informationsteknik, Datorteknik, Electronics Systems

27th IFIP/IEEE International Conference on Very Large Scale Integration

VLSI-SoC 2019
Cusco, ,

Energieffektiv och höghastighets-transmission i optisk fiber kommunikation

VINNOVA, 2018-01-01 -- 2019-12-31.

Ämneskategorier

Datorteknik

Telekommunikation

Elektroteknik och elektronik

Styrkeområden

Informations- och kommunikationsteknik

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Skapat

2019-10-17