Resilient chip multiprocessors with mixed-grained reconfigurability
Artikel i vetenskaplig tidskrift, 2016
This article presents a chip multiprocessor (CMP) design that mixes coarse- and fine-grained reconfigurability to increase core availability of safety-critical embedded systems in the presence of hard errors. The authors conducted a comprehensive design-space exploration to identify the granularity mixes that maximize CMP fault tolerance and minimize performance and energy overheads. The authors added fine-grained reconfigurable logic to a coarse-grained sparing approach. Their resulting design can tolerate 3 times more hard errors than core redundancy and 1.5 times more than any other purely coarse-grained solution.
Pipeline implementation
Serviceability
Adaptable architectures
Multicore
Reconfigurable hardware
Availability
Reliability
Microarchitecture implementation considerations
Single-chip multiprocessor
CMP
Författare
Ioannis Sourdis
Chalmers, Data- och informationsteknik, Datorteknik
Danish Anis Khan
Chalmers, Data- och informationsteknik
Alirad Malek
Chalmers, Data- och informationsteknik, Datorteknik
Stavros Tzilis
Chalmers, Data- och informationsteknik, Datorteknik
G. Smaragdos
C. Strydis
IEEE Micro
0272-1732 (ISSN)
Vol. 36 1 35-45 7006345Ämneskategorier
Datorteknik
DOI
10.1109/MM.2015.7