IntelliCache: Intelligent Cache Systems
Research Project, 2024
– 2026
Purpose and goal
The IntelliCache project will build the Cache-MX IP block on FPGA that will yield a doubling of cache capacity and commit at least 1 server customer.
Expected effects and result
The project targets to demonstrate an increase in the capacity of cache design through inline real-time data compression. The demonstration will happen on a FPGA platform prototype. Increasing the cache capacity has paramount effects in the performance and energy consumption of processor systems given the increasing demands for more memory due to the emerging applications. A doubling of the cache capacity would improve performance by roughly 15% and reduce the energy consumption by about 15% yielding an improvement in performance/watt by 35% (i.e., 1.15/0.85 = 1.35).
Participants
Bhavishya Goel (contact)
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Collaborations
ZeroPoint Technologies AB
Göteborg, Sweden
Funding
VINNOVA
Project ID: 2024-00603
Funding Chalmers participation during 2024–2026