2D-CHARM: Two-dimensional Charge-based Memories

Research Project, 2027 – 2031

Modern computers mainly store information using silicon charge-based memories, but continued progress in memory density and performance is increasingly constrained by silicon’s material limits. Atomically thin two-dimensional (2D) semiconductors have properties that may address some of these constraints. 2D-CHARM will identify the physical mechanisms and feasibility limits that govern whether monolayer 2D semiconductors can enable charge-based memory operation at very small dimensions, and under which conditions they may complement or replace silicon in future memory technologies.

To do this, we will evaluate two memory types through characterization of nanofabricated memory test structures. For DRAM (Dynamic Random Access Memory, the computer’s main working memory), we will study cells where a 2D transistor acts as the on/off switch that must block leakage when data are stored, and determine how device geometry and the semiconductor–insulator interface affect device charge leakage and performance drift. In flash (the long-term memory used in SSDs), we will fabricate test structures using 2D semiconductors and the charge-trap stacks used in modern flash, and map the trade-offs between write speed, retention time and endurance during extended memory operation.

The outcome is a mechanism-based feasibility map that links material properties and device design to memory metrics, exploring the application space of 2D semiconductors in charge-based memory.