DeSyRe will perform research on the design of future reliable Systems-on-Chip (SoCs). These are systems that guarantee continuous and correct operation in the existence of different types of faults. It is a well known fact that various systems are extremely sensitive to faults. Typical examples are medical (i.e. implantable cardiac pacemakers) or automotive systems (i.e. vehicle stability control), in which the shortest stop in operation will cause dramatic damages. Therefore, such applications require a fault-tolerant system, which guarantees correct and reliable functioning at any time.However, as semiconductor technology scales, chips are becoming ever less reliable; prominent reasons for this phenomenon are the sheer number of transistors on a given silicon area and their shrinking device features. As a consequence, fault tolerance, e.g. provided through various redundancy schemes, has an enormously increasing power and performance cost. To make matters worse, power-density is becoming a significant limiting factor for performance and SoC design in general. In the face of such changes in the technological landscape, current solutions for fault-tolerance are expected to introduce an excessive overhead in future SoCs. Attempting to design and manufacture a totally fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the performance and power consumption of a system.DeSyRe will build new, more efficient, adaptive fault-tolerant SoCs delivering a new generation of by design, on-demand reliable systems. Compared to existing approaches, the DeSyRe objective is to reduce the power and performance overheads of fault-tolerance by 10-20%, as well as to improve yield by decreasing the number of defective chips by 10-40%.The above will be achieved through the design of fault-tolerant systems built out of unreliable components, rather than aiming at totally fault-free chips. DeSyRe systems will be on-demand adaptive to various types and densities of faults, as well as to other system constraints and application requirements. For leveraging on-demand adaptation/customization and reliability at reduced cost, a new dynamically reconfigurable substrate will be designed and combined with runtime system software support. The developed design will be demonstrated for two medical SoCs with high reliability constraints and diverse performance and power requirements.The SMEs of the project will exploit the various results of the project in their respective domains. It is expected that they will strengthen their market position and competitiveness having a multiple return on investment. The universities and research organizations will stay on the forefront of research in using the results. The project will strongly contribute in substantiating their prestige in the scientific community. The European citizens will benefit from cheaper hardware and lower power consumption of various consumer goods.
Docent vid Chalmers University of Technology, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
London, United Kingdom
Bristol, United Kingdom
SAN GIULIANO TERME, Italy
Funding Chalmers participation during 2011–2015 with 6,791,672.00 SEK