P4PIM: Principles of power-constrained HPC programming for PIM networks
Research Project, 2021 – 2024

Computer design has traditionally focused on increasing processor speed and memory capacity. This has created a bottleneck between processor and memory, as latencies and bandwidth struggle to accommodate the needs of data-intensive applications. Processing-in-Memory, embodied by products such as the Hybrid Memory Cube, describe an approach to overcome this bottleneck. Combined with silicon interposers, it becomes feasible to build chips with high memory capacity, high bandwidth and low latency. However, this transition requires to adapt the programming model to this new generation of chips. The goal of the P4PIM project is to enable data-intensive HPC on PIM-based systems, by researching the necessary runtime technologies and proposing extensions to widely used programming models.
The project is organized into three phases that will
(1) study how to partition data and collocate it with its opertators,
(2) research how to manage parallelism to meet the power constraints of the PIM systems, and
(3) study runtime and architecture codesign to enable novel organizations across the computer architecture stack.
A breakthrough in methods for partitioning data and managing parallelism in scalable, parallel PIM-based systems is expected to have a high impact and be groundbreaking, even beyond HPC and PIM based systems, making P4PIM´s scientific significance and industrial relevance high.


Miquel Pericas (contact)

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)


Swedish Research Council (VR)

Project ID: 2020-04892
Funding Chalmers participation during 2021–2024


More information

Latest update