New Design of a RSFQ Parallel Multiply-Accumulate Unit

Journal article, 2006

The Multiply-Accumulate Unit (MAC) is a central component of a Successive Interference Canceller, an advanced receiver for W-CDMA base stations. A 4*4 two's complement fixed point RSFQ MAC with rounding to 5 bits has been simulated using VHDL and maximum performance is equal to 24 GMACS (giga multiple-accumulates per second). The clock distribution network has been re-designed from a linear ripple to a binary tree network in order to eliminate data dependence of the clock propagation speed and reduce number of Josephson junctions in clock lines. The 4*4 bits MAC has been designed for the HYPRES 4.5 kA/cm^2 process and its components have been experimentally tested at low frequency: the 5 bit combiner, using an exhaustive test pattern, had margins on DC bias voltage of +-18% and the 4*4 parallel multiplier had margins equal to +-2%.