Customization for an Energy-Efficient Embedded Processor with Flexible Datapath

Licentiate thesis, 2010

Due to diversified demands of customers, embedded processor datapaths have been extended to accept many functional units, thus growing more complex and energy inefficient. For this reason, it is necessary to carefully analyze the characteristics of the specific embedded applications and fine-tune the hardware implementation. This thesis addresses two approaches to the design of an energy-efficient embedded processor with flexible datapaths (FlexCore): The first approach entails customizing the processor by considering data-routing flexibility between datapath units, while the second one deals with integration of accelerators for performance enhancement. The first part of the thesis focuses on a processor design environment that allows for customization of the FlexCore processor. Here, a design space exploration methodology to customize the FlexCore datapath interconnect to a domain of applications, with the goal of reducing energy dissipation, is proposed. The second part of the thesis proposes a high-speed energy-efficient 2-cycle multiply-accumulate architecture, which can act as an accelerator for embedded processors. As an extension to the proposed architecture, a versatile double throughput multiply-accumulate unit for data-intensive computations is proposed. The third part of the thesis deals with a design flow to systematically integrate accelerators into an embedded processor with flexible datapath for performance enhancement. By taking advantage of high-throughput processing, the integrated FlexCore-DTMAC architecture shows a significant improvement in both execution time and energy dissipation. Finally, in addition to the novel solutions for customization of an energy-efficient embedded processor with flexible datapath, some future works are also discussed in the framework of this thesis.