Design and Fabrication of 0/1-Level RF-Via Interconnect for RF-MEMS Packaging Applications
Journal article, 2010
This paper presents the parametric study of RF-via (0-level) and flip-chip bump (1-level) transitions for applications of packaging coplanar RF-MEMS devices. The key parameters were found to be the bumps' and vias' positions and the overlap of the metal pads, which should be carefully considered in the entire two levels of packages. The length of the backside transmission line, determining the MEMS substrate area, showed minor influence on the interconnect performance. With the experimental results, the design rules have been developed and established. The optimized interconnect structure for the two levels of packages demonstrates the return loss beyond 15 dB and the insertion loss within 0.6 dB from dc to 60 GHz.
flip-chip interconnects
packaging
Fabrication
ghz
microelectromechanical devices
interconnections
cpw
microwave technology
Author
L. H. Hsu
Chalmers, Microtechnology and Nanoscience (MC2)
National Chiao Tung University
W. C. Wu
Chalmers, Microtechnology and Nanoscience (MC2)
National Chiao Tung University
E. Y. Chang
National Chiao Tung University
National Cheng Kung University
Herbert Zirath
Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics
Y. C. Wu
National Chiao Tung University
C. T. Wang
National Chiao Tung University
C. T. Lee
National Cheng Kung University
IEEE Transactions on Advanced Packaging
1521-3323 (ISSN)
Vol. 33 1 30-36 5345704Subject Categories (SSIF 2011)
Electrical Engineering, Electronic Engineering, Information Engineering
DOI
10.1109/TADVP.2009.2034137