Verification of Operation Sequences in Process Simulate by Connecting a Formal Verification Tool

Paper in proceeding, 2009

It is very advantages to use virtual techniques for testing and developing new hardware and software systems. It is cost effective since no real machine or manufactory system is needed. It is safe since there are no real components that can be damaged. Simulation is a fast design method since the time can go faster then real time and the machine can be set to desired machine states without time consumption. Novel concepts can be tested prior to manufacturing. However, it is of greatest importance that the virtual model can be trusted so that the results of the development and tests can be directly transferred to a real system without any manual last minute changes. Testing all possible scenarios within a system by simulation is an ambiguous task and is impossible to do with todays complex systems. The present paper introduces a method for combining virtual development and simulation techniques with tools for formal verification methods. The aim is to enable the use of formal verification techniques and by doing that guaranteeing a correct system behavior.