A formal specification language for PLC-based control logic
Paper in proceeding, 2010
Formal verification, using model checking tools, is promising in developing (IEC 61131) industrial control logic. Formal verification requires a formal specification of the properties to be verified. Specifications in model checking tools are typically expressed using temporal logic. However, the standard temporal logic dialects are not well suited for control engineers who do rarely have a background within computer science. In this paper a new dialect of linear temporal logic, ST-LTL, is introduced that intends to be easier to use for control engineers than the existing dialects. The relation of ST-LTL compared to existing temporal logic dialects is analyzed. © 2010 IEEE.
Author
Oscar Ljungkrantz
Chalmers, Signals and Systems, Systems and control
Knut Åkesson
Chalmers, Signals and Systems, Systems and control
Martin Fabian
Chalmers, Signals and Systems, Systems and control
Chengyin Yuan
General Motors
Proceedings of the 8th IEEE International Conference on Industrial Informatics, INDIN 2010; Osaka; 13 July 2010 through 16 July 2010
1935-4576 (ISSN)
1067-1072978-142447300-7 (ISBN)
Subject Categories
Computer and Information Science
Areas of Advance
Production
DOI
10.1109/INDIN.2010.5549591
ISBN
978-142447300-7