Characterization and Exploitation of Silent Loads
Paper in proceeding, 2010
As multicore architectures have hit the mainstream, one of the challenges for future multicore designs is to maintain a high memory bandwidth. To this end, we introduce the concept of silent loads to improve the execution efficiency of memory instructions. We define a load instruction as a silent load (SLD) if there is a value-based association of the requested memory location with a set of registers in the physical register file (RF). If such an association exists, the load instruction can be cancelled, i.e., it is silent. We establish that as many as 32% of all dynamic loads are silent across a set of applications in the desktop domain. We propose a novel micro-architectural scheme to capitalize on SLDs. Our scheme maintains an explicit relation between a set of registers in the physical RF with a set of memory addresses at run-time without compiler support and ISA extension. We show that our scheme improves both performance and performance per watt.