Portable, scalable, per-core power estimation for intelligent resource management
Paper in proceeding, 2010

Performance, power, and temperature are now all first-order design constraints. Balancing power efficiency, thermal constraints, and performance requires some means to convey data about real-time power consumption and temperature to intelligent resource managers. Resource managers can use this information to meet performance goals, maintain power budgets, and obey thermal constraints. Unfortunately, obtaining the required machine introspection is challenging. Most current chips provide no support for per-core power monitoring, and when support exists, it is not exposed to software. We present a methodology for deriving per-core power models using sampled performance counter values and temperature sensor readings. We develop application-independent models for four different (four- to eight-core) platforms, validate their accuracy, and show how they can be used to guide scheduling decisions in power-aware resource managers. Model overhead is negligible, and estimations exhibit 1.1%-5.2% per-suite median error on the NAS, SPEC OMP, and SPEC 2006 benchmarks (and 1.2%-4.4% overall).

per-core power estimation

intelligent resource management

chip multiprocessor systems

power efficiency

application-independent models


Bhavishya Goel

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Sally A McKee

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Roberto Gioiosa

Centro Nacional de Supercomputacion

Karan Singh

Cornell University

Major Bhadauria

Cornell University

Marco Cesati

University of Rome Tor Vergata

International Green Computing Conference, 2010, Chicago, USA

978-1-4244-7612-1 (ISBN)

Areas of Advance

Information and Communication Technology

Subject Categories

Computer Systems





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