A circuit approach to LTL model checking
Paper in proceeding, 2013

This paper presents a method for translating formulas written in assertion languages such as LTL into a monitor circuit suitable for model checking. Unlike the conventional approach, no automata is generated for the property, but instead the monitor is built directly from the property formula through a recursive traversal. This method was first introduced by Pnueli et. al. under the name of Temporal Testers. In this paper, we show the practicality of temporal testers through experimental evaluation, as well as offer a self-contained exposition for how to construct them in manner that meets the requirements of industrial model checking tools. These tools tend to operate on logic circuits with sequential elements, rather than transition relations, which means we only need to consider so called positive testers with no future references. This restriction both simplifies the presentation and allows for more efficient monitors to be generated. In the final part of the paper, we suggest several possible optimizations that can improve the quality of the monitors, and conclude with experimental data.


Koen Lindström Claessen

Chalmers, Computer Science and Engineering (Chalmers), Software Technology (Chalmers)

B. Sterin

13th International Conference on Formal Methods in Computer-Aided Design, FMCAD 2013; Portland, OR; United States; 20 October 2013 through 23 October 2013

978-098356783-7 (ISBN)

Subject Categories

Software Engineering





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