Design and analysis of binary tree static random access memory for low power embedded systems

Journal article, 2014

In the modern portable applications, the embedded systems are required to have low power dissipation. Therefore, SRAM designs are required to achieve both high-performance and low-power for the microprocessors. However, low power design of these memories is highly challenging due to conflicting design requirements of high-performance and robustness under process-voltagetemperature (PVT) variations. In this paper, an architectural-level methodology is proposed for lowpower SRAMs (LPSRAM). In the proposed LPSRAM architecture, the SRAM subsystem is divided into modules, with inter-module connections organized in a binary tree. Due to such organization LPSRAM can achieve low power consumption and dynamic reconfiguration during normal operation mode. We formulate the read/write power, performance and area models of the proposed memory design, which are then substantiated and validated through a number of experiments using CAD tools and HSPICE simulations. We show that LPSRAM can significantly reduce power consumption (by up to 30% in normal operation mode) when compared with traditional SRAM designs at the expense of reasonable area overheads. Moreover, we demonstrate that due to efficient switching architecture LPSRAM offers better robustness under process variations, while retaining high performance. Furthermore, the LPSRAM structure has strong potential to be built with testability. The memory nodes can be tested in parallel, since all the memory modules are located in the bottom level of the binary tree. Within the proposed testable LPSRAM architecture, a reduction in testing time and power can be achieved.