An 802.11p Cross-Layered Pilot Scheme for Time- and Frequency-Varying Channels and Its Hardware Implementation
Journal article, 2016
Robust channel estimation in IEEE 802.11p systems in highly time- and frequency-varying vehicular channels, in combination with long data packets, is a challenging task due to the ill-suited pilot pattern. Solutions of increased receiver complexity that use decision feedback and iterative decoding have been proposed to overcome the difficulty in robust channel estimation. In this paper, a cross-layered method to introduce complementary training symbols into an 802.11p frame is proposed. In the proposed approach, known bits are multiplexed with the data in higher layers, and a modified receiver can utilize these bits as training data for improved channel estimation. A standard receiver treats these bits as data and passes them to the higher layers, where they can be removed, making the method compatible with standard 802.11p transceivers. A software/firmware update of the higher layers is needed in a standard receiver to remove the multiplexed bits. A modified receiver with low-complexity channel estimation schemes that utilizes the complementary training symbols is implemented in a field-programmable gate array (FPGA) platform. Frame error rate (FER) measurements have been performed by interfacing the hardware implementation with a channel emulator. The measurement results follow the computer simulation results, validating the hardware implementation. Moreover, measurement results show that the modified receiver follows the performance of an ideal receiver that has full knowledge of the channel (with only an offset in signal-to-noise ratio (SNR)) and significantly outperforms the commercial 802.11p transceiver we tested.
field programmable gate array (FPGA) implementation
orthogonal frequency-division multiplexing (OFDM)