Main Memory in HPC: Do We Need More or Could We Live with Less?
Journal article, 2017

An important aspect of High-Performance Computing (HPC) system design is the choice of main memory capacity. This choice becomes increasingly important now that 3D-stacked memories are entering the market. Compared with conventional Dual In-line Memory Modules (DIMMs), 3D memory chiplets provide better performance and energy efficiency but lower memory capacities. Therefore, the adoption of 3D-stacked memories in the HPC domain depends on whether we can find use cases that require much less memory than is available now. This study analyzes the memory capacity requirements of important HPC benchmarks and applications. We find that the High-Performance Conjugate Gradients (HPCG) benchmark could be an important success story for 3D-stacked memories in HPC, but High-Performance Linpack (HPL) is likely to be constrained by 3D memory capacity. The study also emphasizes that the analysis of memory footprints of production HPC applications is complex and that it requires an understanding of application scalability and target category, i. e., whether the users target capability or capacity computing. The results show that most of the HPC applications under study have per-core memory footprints in the range of hundreds of megabytes, but we also detect applications and use cases that require gigabytes per core. Overall, the study identifies the HPC applications and use cases with memory footprints that could be provided by 3D-stacked memory chiplets, making a first step toward adoption of this novel technology in the HPC domain.

high-performance computing

production HPC applications

HPL

Memory capacity requirements

Author

D. Zivanovic

Centro Nacional de Supercomputacion

M. Pavlovic

Centro Nacional de Supercomputacion

ASML Netherlands BV

M. Radulovic

Centro Nacional de Supercomputacion

H. Shin

Centro Nacional de Supercomputacion

J. Son

Centro Nacional de Supercomputacion

Sally A McKee

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

P. M. Carpenter

Samsung

P. Radojkovic

Samsung

Sally A McKee

Chalmers University of Technology

Transactions on Architecture and Code Optimization

1544-3566 (ISSN) 1544-3973 (eISSN)

Vol. 14 Article nr 3-

Areas of Advance

Information and Communication Technology

Subject Categories

Computer and Information Science

Roots

Basic sciences

DOI

10.1145/3023362