Integrated on-chip solid state capacitor based on vertically aligned carbon nanofibers, grown using a CMOS temperature compatible process
Journal article, 2018

Complete miniaturized on-chip integrated solid-state capacitors have been fabricated based on conformal coating of vertically aligned carbon nanofibers (VACNFs), using a CMOS temperature compatible micro-fabrication processes. The 5 mu m long VACNFs, operating as electrode, are grown on a silicon substrate and conformally coated by aluminum oxide dielectric using atomic layer deposition (ALD) technique. The areal (footprint) capacitance density value of 11-15 nF/mm(2) is realized with high reproducibility. The CMOS temperature compatible microfabrication, ultra-low profile (less than 7 mu m thickness) and high capacitance density would enables direct integration of micro energy storage devices on the active CMOS chip, multi-chip package and passives on silicon or glass interposer. A model is developed to calculate the surface area of VACNFs and the effective capacitance from the devices. It is thereby shown that 71% of surface area of the VACNFs has contributed to the measured capacitance, and by using the entire area the capacitance can potentially be increased.







Muhammad Amin

Chalmers, Microtechnology and Nanoscience (MC2), Electronics Material and Systems

R. Andersson

Smoltek AB

Vincent Desmaris

Smoltek AB

Peter Enoksson

Chalmers, Microtechnology and Nanoscience (MC2), Electronics Material and Systems

Wallenberg Wood Science Center (WWSC)

Solid-State Electronics

0038-1101 (ISSN)

Vol. 139 75-79

Areas of Advance

Information and Communication Technology

Nanoscience and Nanotechnology (SO 2010-2017, EI 2018-)




Materials Science

Driving Forces

Innovation and entrepreneurship

Subject Categories

Materials Chemistry

Electrical Engineering, Electronic Engineering, Information Engineering


Nanofabrication Laboratory



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