System Level Partitioning for Embedded Systems
Paper in proceeding, 2017

Platforms with different computation resource, e.g. CPUs and FPGAs, become one of the first choices to deploy performance-requiring embedded applications. On this technology, functionalities can be implemented either as hardware (HW) or software (SW) components. Here, we extend the MultiPar methodology to support the selection of optimal partitioning solutions with respect to system properties. We show the feasibility of the proposed methodology and validate the composition rules for properties used in the partitioning decision process.

Author

G. Sapienza

ABB

N. Meli

ABB

J. Eriksson

ABB

R. Jansson

ABB

T. Seceleanu

ABB

Ivica Crnkovic

Chalmers, Computer Science and Engineering (Chalmers), Software Engineering (Chalmers)

Proceedings International Computer Software and Applications Conference

0730-3157 (ISSN)

597-602
978-1-5386-0367-3 (ISBN)

41st IEEE Annual Computer Software and Applications Conference (COMPSAC)
Torino, Italy,

Subject Categories

Software Engineering

Embedded Systems

Computer Systems

DOI

10.1109/COMPSAC.2017.226

More information

Latest update

10/28/2022