Participatory verification of railway infrastructure by representing regulations in RailCNL
Paper in proceeding, 2017

© Springer International Publishing AG 2017. Designs of railway infrastructure (tracks, signalling and control systems, etc.) need to comply with comprehensive sets of regulations describing safety requirements, engineering conventions, and design heuristics. We have previously worked on automating the verification of railway designs against such regulations, and integrated a verification tool based on Datalog reasoning into the CAD tools of railway engineers. This was used in a pilot project at Norconsult AS (formerly Anacon AS). In order to allow railway engineers with limited logic programming experience to participate in the verification process, in this work we introduce a controlled natural language, RailCNL, which is designed as a middle ground between informal regulations and Datalog code. Phrases in RailCNL correspond closely to those in the regulation texts, and can be translated automatically into the input language of the verifier. We demonstrate a prototype system which, upon detecting regulation violations, traces back from errors in the design through the CNL to the marked-up original text, allowing domain experts to examine the correctness of each translation step and better identify sources of errors. We also describe our design methodology, based on CNL best practices and previous experience with creating verification front-end languages.

Author

Bjørnar Luteberget

Railcomplete AS

John J. Camilleri

University of Gothenburg

Christian Johansen

University of Oslo

Gerardo Schneider

University of Gothenburg

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

03029743 (ISSN) 16113349 (eISSN)

Vol. 10469 LNCS 87-103

15th IEEE International Conference on Software Engineering and Formal Methods, SEFM 2017
Trento, Italy,

Subject Categories

Language Technology (Computational Linguistics)

Design

Embedded Systems

DOI

10.1007/978-3-319-66197-1_6

More information

Latest update

11/29/2021