A 10-mW mm-wave phase-locked loop with improved lock time in 28-nm FD-SOI CMOS

Journal article, 2019

© 2019 IEEE. This paper presents a millimeter-wave (mm-wave) phase-locked loop (PLL), with an output frequency centered at 54.65 GHz. It demonstrates a mode-switching architecture that considerably improves the lock time, by seamlessly switching between a low-noise mode and a fast-locking mode that is only used during settling. The improvement is used to counteract the increased lock-time caused by cycle-slips that results from using a high reference frequency of 2280 MHz, which is several hundred times the loop bandwidth. Such a reference frequency alleviates the noise requirements on the PLL and is readily available in 5G systems, from the radio frequency PLL. The mm-wave PLL is implemented in a low-power 28-nm fully depleted silicon-on-insulator CMOS process, and its active area is just 0.19 mm 2 . The PLL also features a novel double injection-locked divide-by-3 circuit and a charge-pump mismatch compensation scheme, resulting in state-of-the-art power consumption, and jitter performance in the low-noise mode. In this mode, the in-band phase noise is between-93 and-96 dBc/Hz across the tuning range, and the integrated jitter is between 176 and 212 fs. The total power consumption of the mm-wave PLL is only 10.1 mW, resulting in a best-case PLL figure-of-merit (FOM) of-245 dB. The lock time in low-noise mode is up to 12μs, which is improved to 3μs by switching to the fast-locking mode, at the temporary expense of a power consumption increase to 15.1 mW, an integrated jitter increase to between 245 and 433 fs, and an FOM increase to between-235 and-240 dB.