Performance Analysis and Modelling of Concurrent Multi-access Data Structures
Paper in proceeding, 2022

The major impediment to scaling concurrent data structures is memory contention when accessing shared data structure access-points, leading to thread serialisation, hindering parallelism. Aiming to address this challenge, significant amount of work in the literature has proposed multi-access techniques that improve concurrent data structure parallelism. However, there is little work on analysing and modelling the execution behaviour of concurrent multi-access data structures especially in a shared memory setting. In this paper, we analyse and model the general execution behaviour of concurrent multi-access data structures in the shared memory setting. We study and analyse the behaviour of the two popular random access patterns: shared (Remote) and exclusive (Local) access, and the behaviour of the two most commonly used atomic primitives for designing lock-free data structures: Compare and Swap, and, Fetch and Add. We model the concurrent multi-accesses by splitting the thread execution procedure into five logical sessions: i) side-work, ii) access-point search iii) access-point acquisition, iv) access-point data acquisition and v) access-point data operation. We model the acquisition of an access-point, as a system of closed queuing networks with parallel servers, and data acquisition in terms of where the data is located within the memory system. We evaluate our model on a set of concurrent data structure designs including a counter, a stack and a FIFO queue. The evaluation is carried out on two state of the art multi-core processors: Intel Xeon Phi CPU 7290 with 72 physical cores and Intel Xeon E5-2695 with 14 physical cores. Our model is able to predict the throughput performance of the given concurrent data structures with 80% to 100% accuracy on both architectures.

performance modelling

data structures

concurrency

parallel programming

queuing theorem

multi-access

lock-free

locality

parallelism

multi-core

semantic relaxation

cache

Author

Adones Rukundo

Chalmers, Computer Science and Engineering (Chalmers), Networks and Systems (Chalmers)

Aras Atalar

Chalmers, Computer Science and Engineering (Chalmers), Networks and Systems (Chalmers)

Philippas Tsigas

Network and Systems

Annual ACM Symposium on Parallelism in Algorithms and Architectures

Vol. SPA 22 333-344
9781450391467 (ISBN)

34th ACM Symposium on Parallelism in Algorithms and Architectures, SPAA 2022
Philadelphia, USA,

Subject Categories

Computer Engineering

Computer Science

Computer Systems

DOI

10.1145/3490148.3538578

More information

Latest update

3/27/2024