Procedure for switching loss determination in an oscillatory environment of GaN FETs in a half-bridge connection

Paper in proceeding, 2024

This paper presents a circuit-level analysis aimed at a rapid switching loss determination in a half-bridge connection utilizing Gallium-nitride field-effect transistors (GaN FETs) in the presence of parasitic elements. A thorough investigation is carried out into the mechanism of oscillations in the gate loop and commmutation loop and a procedure to reduce the current decline during the freewheeling state is presented. Simulation results are provided to demonstrate and validate circuit-level analysis graphically. It is revealed that gate loop oscillations show dependency on the commutation loop due to common source inductance and Miller capacitance. A larger gate resistance could damp oscillations fast but possibly increase the peak value, leading to gate breakdown. Additionally, a power loss analysis of GaN FETs in reverse conduction status reveals a reduction in losses compared to conventional double pulse test (DPT) methods, further steadying the load current and favoring switching loss measurement of GaN FETs at the same level.