Reliable and Energy Optimized Task Mapping for Heterogeneous Multi-Core NoC Based on Partial Task Duplication and Multi-Path Routing

Journal article, 2025

The increasing integration of heterogeneous processors on a chip presents significant challenges for efficient management in Multi-Processor System-on-Chip (MPSoC) platforms. Network-on-Chip (NoC) architectures offer a flexible and scalable interconnection paradigm through router-based communication. However, mapping dependent, real-time tasks in NoC environments critically affects data processing and transmission efficiency. An optimized task mapping scheme must address constraints such as real-time deadlines, energy consumption, and reliability, which are key metrics for modern NoCs. Existing approaches often overlook the complex interplay between communication paths and their associated energy costs, resulting in suboptimal resource utilization. This paper proposes a comprehensive task mapping framework that jointly optimizes energy efficiency and reliability by integrating Dynamic Voltage and Frequency Scaling (DVFS), multi-path data routing, task allocation, scheduling, and partial task duplication. We formulate the problem as a complex combinatorial optimization task and transform it into a solvable form with reduced computational complexity. Simulation results demonstrate that the proposed method achieves superior energy efficiency by reducing energy consumption by up to 39.7%, reducing computation time, and improving task schedulability compared to existing state-of-the-art approaches.