Integrated Variable-Gain and CMOS Millimeter-Wave Amplifiers

Doctoral thesis, 2008

Variable Gain Amplifier finds extensive use in the high frequency demonstrators specially those operating in the millimeter-wave regions and beyond where the incoming RF signal level can have wide variations. To maintain a constant signal level an IF VGA has been designed that can offer a dynamic variation of gain as much as 45 dB together with a high maximum gain and a low noise figure. The first part of the thesis starts with theoretical as well as analytical investigations of designing a VGA based on the various possible topologies. Feasibility of implementing the Monolithic Microwave Integrated Circuit (MMIC) version of the IF VGA is then followed. Foundry based High Electron Mobility Transistors (HEMT) have been used for the realization of the circuit. Two high gain, low noise, VGA have been designed and characterized based on series feedback and parallel feedback topologies. A 45 dB of gain control and a maximum gain of 47 dB have been achieved with the series feedback VGA whereas the corresponding figures for the parallel feedback VGA are, 55 dB and 35 dB, respectively. The circuits were designed for a center frequency of 2.5 GHz. The noise figure for the series feedback VGA is 0.81 dB in the highest gain mode and for the parallel feedback VGA it is 0.86 dB. The -1 dB compression and OIP3 for the series feedback VGA are -7.2 dBm and +2 dBm, respectively. The corresponding figures for the parallel feedback VGA are -9.5 dBm and +1.3 dBm, respectively. The second part of the thesis discusses the design and characterization of small signal amplifiers using a foundry based submicron CMOS processes both with the 45 nm and the 90 nm technology. The latest state-of-the-art 45 nm CMOS process i.e the bulk CMOS and the FinFET have recently got much attention of the researchers. A brief investigation on ft for both the devices have been carried out followed by a concise overview on the technology. Maximum achievable value of ft for 45 nm bulk CMOS is of the order of 200 GHz. For FinFET this value is around 100 GHz. Two wiring options i.e. the Back-End-Of-Line (BEOL) and the post process Wafter-Level-Packaging (WLP) have been considered for transmission line as well as passive implementations and are discussed in some details. It is then followed by the MMIC implementations of the small signal amplifiers. Foundry provided models as well as in-house developed models are used in the circuit analysis. The 40 GHz amplifier designed in the back end of 90 nm CMOS gave a measured gain of 6 dB at 40 GHz. The corresponding measured noise figure is 7.8 dB. The measured -1 dB compression is -5.5 dB referred to the output. Using the same technology node, the 20 GHz amplifier gave a gain of 5.8 dB with the measured NF of 5.4 dB. The non linear measurement gave -1 dB compression of +1 dB and an IP3 of +10 dBm both referred to the output. Amplifiers designed in the latest 45 nm CMOS technology, shows promising results with an achievable gain as much as 12 dB at 90 GHz.