Functional Programming Enabling Flexible Hardware Design at Low Levels of Abstraction

Doctoral thesis, 2008

Continuous down-scaling of sizes in VLSI circuits causes low-level electrical phenomena to become more and more prominent performance stoppers in modern chip technologies. This forces designers to work at a lower level of abstraction than desired in order to gain control over these effects. The most dominating contributors to low-level performance problems are the routing wires, which are used to connect the gates (computational units) on the chip. Hardware description languages (HDLs) – which naturally strive for generality and reusablility – tend to focus on higher levels of abstraction. This means that the low-level effects are not visible and thus very hard to control. To date, we are not aware of any HDL that allows control over the effects of routing wires in a really useful way, so when high-performance is crucial, designers are left to interfacing directly with CAD tools for physical chip design. This thesis presents a flexible wire-aware design system called Wired and shows how it has developed from a preliminary idea to a relatively mature system that can now be tried on real-world challenges. The present Wired builds upon the existing HDL Lava, and extends it with: (a) finer control over geometry, (b) support for geometrical refinement, (c) more accurate performance models, (d) basic wire-awareness, and (e) support for descriptions with abstract signal flow. Wired is implemented in the functional programming language Haskell. It has a simple modular implementation consisting of three separate main components: (1) The Lava library, for representing the structural circuit view, (2) a new monadic library for expressing layout, and (3) a new library for light-weight logical variables. The system is used to improve the accuracy of an algorithm for searching for fast, low-power parallel prefix networks. More experiments are needed in order to reach industrially applicable results, but the main contribution here is the fact that physically aware design exploration is actually achievable at this level of flexibility. Although not yet tested on industrial problems, Wired seems like a very promising system that has a good potential of reducing the effort of generating high-quality layouts of complex circuits.