Compression Techniques for Improved Bandwidth and Static Code Size in Computer Systems
Doctoral thesis, 2008

Technological improvements in integrated circuits have for a long time allowed the performance of computer chips to grow exponentially, allowing for more and more advanced systems. Unfortunately, the I/O-pins connecting the processor core/cores with memory and other devices have not seen the same rate of improvement. In this thesis I study the opportunities and challenges with using compression to help solve some of the challenges that have emerged. These include reducing the bandwidth needed and the static code size. The first part of the thesis addresses data-link compression. By studying the data transferred between the last-level cache and main memory, several types of localities that can be used to compress the data are identified. Current state-of-the-art compression techniques are analyzed in the context of this categorization. Using this categorization, I show that it is possible to combine techniques that work on different types of locality into a more efficient compression algorithm. Moreover, I show how stateful compression schemes can be implemented in multi-node systems. This thesis also considers efficient program representation. In most programs, identical sequences of instructions often appear in several places, making dictionary based compression an efficient scheme for reducing the static code size. In this thesis I propose a new, more flexible scheme in which similar sequences of instructions can be represented by the same dictionary entry and executed with low hardware overhead. Finally, a code compression scheme targeting wide instruction formats is presented. The scheme is based on dynamic look-up tables, which allow the compiler to adapt the compression to different phases of the application. Also presented is a methodology for dimensioning the decompression engine and an algorithm for generating compressed programs that dynamically manage the look-up tables with little run-time performance overhead. The compression scheme is evaluated using FlexCore, an architecture with exposed datapath control, and shown to efficiently reduce the control-bits of the instruction word by more than 50%.

instruction decoding

data link compression

code compression

Computer architecture

HB1
Opponent: Prof. Andre Seznec, IRISA, France

Author

Martin Thuresson

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Value-Cache Based Compression Schemes for Multiprocessors

18th International Conference on Computer Architecture and High Performance Computing,; (2006)

Journal article

Evaluation of Extended Dictionary-Based Static Code Compression Techniques

ACM Computing Frontiers,; (2005)

Paper in proceedings

Accommodation of the Bandwidth of Large Cache Blocks using Cache/Memory Link Compression

International Conference on Parallel Processing,; (2008)

Paper in proceedings

Memory Link Compression Schemes: A Value Locality Perspective

IEEE Transactions on Computers,; (2008)

Journal article

Subject Categories

Computer Engineering

ISBN

978-91-7385-156-5

Doktorsavhandlingar vid Chalmers tekniska högskola. Ny serie: 2837

Technical report D - Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University: 44

HB1

Opponent: Prof. Andre Seznec, IRISA, France

More information

Created

10/8/2017