High efficiency power amplifiers for wireless communications

Licentiate thesis, 2009

This thesis presents state-of-the-art high efficiency harmonically-tuned power amplifiers (PAs) and investigates the characteristics and potentials of such amplifiers in two of the most promising efficiency enhancement techniques, dynamic supply and load modulation. In this work, a 10 W LDMOS harmonically-tuned PA with 80% power-added-efficiency (PAE) is realized at 1 GHz. To the author's knowledge, this is the highest PAE reported for high power LDMOS PAs at frequencies higher than 0.9 GHz. A bare-die design approach is chosen facilitating the harmonic load impedance tuning at bare-die reference plane. Another 1 GHz high performance power amplifier using a packaged transistor, delivering 20 W with 69% PAE and 15 dB gain, is also presented. This PA is based on a current mode class-D (CMCD) topology taking advantage of the push-pull configuration as one more degree of freedom for optimization of the harmonic load impedances. The gain and efficiency result achieved presents state-of-the-art for this topology using high power LDMOS transistors. The importance of harmonic load impedance tuning, popular at few GHz frequencies, is then investigated at 35 GHz using GaAs mHEMT MMIC technology. It is shown that the second harmonic load impedance is very critical for high efficiency performance even at such high frequencies. The MMIC PA implemented, demonstrates an output power of 14 dBm with a small-signal gain of 14 dB and a maximum PAE of 43%. In the second part of this thesis, static characteristics of LDMOS and GaN PAs for use in dynamic supply modulation transmitter architectures are investigated. It is found that, by an optimum simultaneous control of PAs input power and output supply voltage, PAE can be significantly improved compared to when a fixed supply voltage is applied. The improvement at 10 dB back-off is about 35 and 50 percentage units for LDMOS and GaN PAs, respectively. Moreover, the potential of high power LDMOS PAs for use in varactor-based dynamic load modulation transmitter architectures is investigated by load-pull measurements. It is shown that the efficiency of the PAs at 10 dB back-off can be improved by about 25 percentage units by optimal co-control of input power and load impedance. It is proposed in this thesis to use the presented characterization results, both for dynamic supply and load modulation architectures, to extract a measurement-based simplified and static inverse-model of the PAs. Such a model is very useful for identification of efficiency optimized controlling schemes and estimation of the system level performance and requirements for the key building blocks in each of the techniques. The usefulness of this approach is in this work demonstrated for the dynamic supply modulation case.