Zero-Value Caches: Cancelling Loads that Return Zero
Report, 2009

The speed gap between processor and memory continues to limit performance. To address this problem, we explore the potential of eliminating Zero Loads — loads accessing memory locations that contain the value “zero” — to improve performance and energy dissipation. Our study shows that such loads comprise as many as 18% of the total number of dynamic loads. We show that a significant fraction of zero loads ends up on the critical memory-access path in out-of-order cores. We propose a non-speculative microarchitectural technique — Zero-Value Cache (ZVC) — to capitalize on zero loads and explore critical design options of such caches. We show that with modest investment (typically a 576-byte structure), we can obtain speedups up to 78% and reduce the overall energy dissipation up to 39%. Most importantly, zero-value caches never cause performance loss.

Load Criticality

Zero-Value Cache

Load Scheduling

Frequent Value Locality

Zero Load

Author

Mafijul Islam

Chalmers, Computer Science and Engineering (Chalmers)

Sally A McKee

Chalmers, Computer Science and Engineering (Chalmers)

Per Stenström

Chalmers, Computer Science and Engineering (Chalmers)

Zero Loads: Canceling Load Requests by Tracking Zero Values

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT,; Vol. 310(2008)p. 16-23

Paper in proceedings

Subject Categories

Computer Engineering

More information

Created

10/7/2017