RSFQ Parallel Multiplier
Conference contribution, 2003

This work presents the design of RSFQ parallel multiplier suitable for implementation of the superconducting digital signal processor for interference cancellation in 3G cellular systems. We have designed the parallel multiplier which consists of N M-bits serial adders based on the T1 cells for M ×N sign multiplication. This multiplier consumes 74×M×N Josephson junctions. The 2-bit and 4-bit parallel multipliers have been designed for TRW’s 8 kA/cm2 process. The maximum VHDL simulated clock speed and one bit effective area are 39 GHz and 300 × 300 μm2 correspondingly.

Multiplier

RSFQ

Parallel

Author

Irina Kataeva

Chalmers, Microtechnology and Nanoscience (MC2), Solid State Electronics

Henrik Engseth

Chalmers, Microtechnology and Nanoscience (MC2), Solid State Electronics

Elena Tolkacheva

Chalmers, Microtechnology and Nanoscience (MC2), Solid State Electronics

Anna Kidiyarova-Shevchenko

Chalmers, Microtechnology and Nanoscience (MC2), Solid State Electronics

Applied Superconductivity 2003, EUCAS sorrento Italy, conference series number 181

Subject Categories

Other Engineering and Technologies not elsewhere specified

Other Electrical Engineering, Electronic Engineering, Information Engineering

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Created

10/6/2017