Characterization and Exploitation of Narrow-Width Loads:The Narrow-Width Cache Approach
Paper in proceedings, 2010

This paper exploits small-value locality to accelerate the execution of memory instructions. We find that narrow-width loads (NWLDs) — loads with small-value operands of 8 bits or less — comprise 26% of all executed loads across 40 applications of the SPEC benchmark suites. We establish that the frequency of NWLDs are almost independent of compiler and input data. We introduce narrow-width caches (NWC) to cache small-value memory words. NWCs provide a significant speedup for several memory-intensive applications with a negligible chip-area overhead. NWCs also reduce the overall energy dissipation and memory traffic.

Narrow-Width Cache

Narrow-Width Load

Small Value Locality

Author

Mafijul Islam

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Per Stenström

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

IEEE/ACM International Conference on Compilers, Architecture, and Synthesis of Embedded Systems (CASES 2010)

227-236

Subject Categories

Computer Engineering

DOI

10.1145/1878921.1878955

ISBN

978-160558903-9

More information

Created

10/7/2017