Multi-Mode Datapath Circuits for Flexible and Energy-Efficient Computing

Doctoral thesis, 2013

Tailored to run domain-specific applications under very strict constraints on, for example, real-time performance and power dissipation, embedded systems rarely can be implemented on general-purpose computing platforms. Rather, the embedded processor's architecture and implementation technology should be fine tuned to the needs of the particular embedded system. However, this is not possible since system complexities are booming, while system implementation resources are limited. Thus, the design of an embedded system is bound to result in tradeoffs between several conflicting requirements. As we will show, to some extent, multi-mode circuits can facilitate these tradeoffs and offer new embedded processor configurations. In this thesis, several approaches to designing energy-efficient embedded processor datapaths are proposed. The overall thesis theme is multi-mode datapath circuits, which are circuits that can operate in different modes, allowing for configuration and adaptation to the applications currently running on the processor. While the main contributions of this thesis are on architecture and circuitry of multi-mode datapath circuits, the thesis also considers processor integration and energy-aware design exploration. The first part of the thesis presents the existing FlexCore processor design environment, which enables holistic processor system evaluations of, for example, multi-mode circuits. Beside a design exploration methodology that allows for application customization, we demonstrate processor integration of a multi-mode cyclic-redundancy-checking (CRC) accelerator. The second part of the thesis concentrates on high-speed and energy-efficient multiply-accumulate (MAC) architectures, which can accelerate signal processing applications of embedded processors, leading to significant energy savings at the application level. In the third and last part, the technique of power gating is applied to exploit computing idle times and unused hardware in narrow-width computation of datapath circuits for leakage energy reductions.