Measurement, Modeling, and Characterization for Energy-Efficient Computing
Doctoral thesis, 2016
The ever-increasing ecological footprint of Information Technology (IT) sector coupled with adverse effects of high power consumption on electronic circuits has increased the significance of energy-efficient computing in the last decade. Making energy-efficient computing a norm rather than an exception requires that system designers and programmers understand the energy implications of their design and implementation choices. This necessitates a detailed view of system’s energy expenditure and/or power consumption. We explore this aspect of energy-efficient computing in this thesis through power measurement, power modeling, and energy characterization.
First, we present a quantitative comparison between power measurement data collected for computer systems using four techniques: a power meter at wall outlet, current
transducers at ATX power rails, CPU voltage regulator’s current monitor, and Intel’s proprietary RAPL (Running Average Power Limit) interface. We compare them for accuracy, sensitivity and accessibility.
Second, we present two different methodologies to model processor power consumption. The first model estimates power consumption at the granularity of individual
cores using per-core performance events and temperature sensors. We validate the methodology on six different platforms and show that our model estimates power consumption with high accuracy across all platforms consistently. To understand the energy expenditure trends across different frequencies and different degrees of parallelism, we need to model power at a much finer granularity. The second power model addresses this issue by estimating static and dynamic power consumption for individual cores and the uncore. We validate this model on Intel’s Haswell platform for single-threaded and multi-threaded benchmarks. We use this power model to characterize energy efficiency of frequency scaling on Haswell microarchitecture and use the insights to implement
a low overhead DVFS scheduler. We also characterize the energy efficiency of thread scaling using the power model and demonstrate how different communication parameters
and microarchitectural traits affect application’s energy when it scales.
Finally, we perform detailed performance and energy characterization of Intel’s Restricted
Transactional Memory (RTM).We use TinySTM software transactional memory
(STM) system to benchmark RTM’s performance against competing STM alternatives.
We use microbenchmarks and STAMP benchmark suite to compare RTM an STM performance
and energy behavior. We quantify the RTM hardware limitations and identify
conditions required for RTM to outperform STM.
EB, EDIT Building, Chalmers University of Technology
Opponent: Dr. Russ Joseph, Associate Professor, Northwestern University, USA