Verified compilation of CakeML to multiple machine-code targets
Paper in proceeding, 2017

This paper describes how the latest CakeML compiler supports verified compilation down to multiple realistically modelled target architectures. In particular, we describe how the compiler definition, the various language semantics, and the correctness proofs were organised to minimize target specific overhead. With our setup we have incorporated compilation to four 64-bit architectures, ARMv8, x86-64, MIPS-64, RISC-V, and one 32-bit architecture, ARMv6. Our correctness theorem allows interference from the environment: the top-level correctness statement takes into account execution of foreign code and per-instruction interference from external processes, such as interrupt handlers in operating systems. The entire CakeML development is formalised in the HOL4 theorem prover.

Verified assembly


Compiler verification


Anthony C. J. Fox

University of Cambridge

Magnus Myreen

Software Technology (Chalmers)

Yong Kiam Tan

Carnegie Mellon University (CMU)

R. Kumar

University of New South Wales (UNSW)

Proceedings of the 6th ACM SIGPLAN Conference on Certified Programs and Proofs, {CPP} 2017

978-1-4503-4705-1 (ISBN)

Areas of Advance

Information and Communication Technology

Subject Categories

Software Engineering





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