Accurate Leakage-Conscious Architecture-Level Power Estimation for SRAM-based Memory Structures
Doctoral thesis, 2007
SRAM Power Modeling
Deep Submicron
Power-Performance Estimation Tool
VLSI
Power Estimation
DSP Architecture
CMOS
Cache Power Modeling
Author
Minh Quang Do
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration
International Symposium on Quality Electronic Design (ISQED),;(2006)
Paper in proceeding
Table-Based Total Power Consumption Estimation of Memory Arrays for Architects
Lecture Notes in Computer Science (LNCS) , Springer Verlag,;Vol. 3254(2004)p. 869-878
Paper in proceeding
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays
8th International Symposium on Quality Electronic Design (ISQED’07),;(2007)p. 185 - 191
Paper in proceeding
Subject Categories
Other Electrical Engineering, Electronic Engineering, Information Engineering
ISBN
978-91-7291-968-6
Doktorsavhandlingar vid Chalmers tekniska högskola. Ny serie: 2649
HC1, Hörsalsvägen, Chalmers
Opponent: Prof. David Brooks, Division of Engineering and Applied Science, Harvard University, Cambridge, Massachusetts, USA