Balanced active frequency multipliers in D and G bands using 250nm InP DHBT technology
Paper in proceeding, 2017

A wideband balanced active frequency doubler at Dband (110–170 GHz) and a frequency tripler at G-band (140–220 GHz) is presented. The circuits are implemented in a 250nm InP DHBT technology with ft/fmax 350/600 GHz respectively. The experimental results of the frequency doubler exhibit an output power of 4.2 dBm with 3-dB output bandwidth from 120 to 158 GHz corresponding to 27.3 % relative bandwidth. The power efficiency is 11.9 % at 124 GHz output and 5 dBm input power. The doubler chip consumes a dc-power of 19 mW and the chip dimension is 0.45 × 0.4 mm2. The tripler chip can provide output power of 3.8 dBm and has 3-dB output bandwidth of 27 GHz from 162–189 GHz. The balanced topology and band pass filter were utilized in tripler circuit for harmonic suppression. The fundamental- and second-harmonic suppressions are better than 20 dBc and 28 dBc, respectively. The dc power consumption is 26 mW. The chip surface is 0.9 × 0.4 mm2.



Marchand balun






Sona Carpenter

Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics

Zhongxia Simon He

Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics

Herbert Zirath

Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics

2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS),

2374-8443 (eISSN)

Subject Categories

Communication Systems

Other Electrical Engineering, Electronic Engineering, Information Engineering



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