Millimeter-wave Transceiver ICs for Ultrahigh Data Rate Communications Using Advanced III-V and Silicon Technologies
Doctoral thesis, 2018
Today’s main driving parameter for radio transceiver research is the ability to provide high capacity while maintaining low cost, small form factor, and low power consumption. Direct conversion architectures (due to the feasibility of monolithic integration) at millimeter-wave (due to wideband availability) have attracted large interest in recent years because of their potential to meet these demands. The communication system operating at frequencies above 100 GHz enabling 10-100 Gbit/s wireless communication in various applications ranging from personal area networks for portable electronic devices, 4G and 5G mobile communication infrastructure, high data rate backhaul, real-time transmission of high-definition videos, short range chip to chip communication (wireless in a box), long-range high-speed communication (using phased arrays), and >40 Gbit/s transmission over dielectric waveguide is of interest in this thesis. However, it is a challenge to design and implement millimeter-wave transceivers that can utilize such wideband effectively for the high data transmission.
This thesis addresses the design challenges and implementation at the individual circuit building blocks of the RF front-end as well as system level considerations for the realization of a fully integrated monolithic microwave integrated (MMICs) transmitter (TX) and receiver (RX) circuits at 110-170 GHz (D-band) in III-V 250 nm indium phosphide double heterojunction bipolar transistor (InP DHBT) and commercial 130 nm SiGe BiCMOS technologies.
The research described in this thesis is focused on the design and characterization of a direct conversion in-phase/quadrature-phase (I/Q) modulator and demodulator, frequency multiplier circuits and integration of fully integrated transceiver chipsets demonstrating the highest RF and IF bandwidths at this frequency to date. The TX/RX chipset consists of an X3 LO frequency multiplier integrated with an I/Q modulator/demodulator and a low-noise amplifier (LNA)/power amplifier (PA). This integration allows us to design the oscillator at one third of the fundamental D-band LO frequency. The chosen design simplifies the packaging of the TX/RX chips and hence reduces the cost and power consumption. A 110–170 GHz RF amplifier is used to improve the noise figure of the RX chip and to increase the gain and transmitted power for the TX chip.
The chipset is multifunctional and can be used in both homodyne and heterodyne architectures supporting high data rate transmission using wide modulation bandwidth and spectral-efficient modulation formats. For QPSK and 64 QAM modulation schemes, the measured data-rates using this chipset are 48 Gbit/s in homodyne mode and 18 Gbit/s in heterodyne mode, respectively. At the time of writing this thesis, this is the highest data-rate reported in the literature for fully integrated wireless systems in the D-band.
The main interest of the work is in real time wireless data traffic transmission on designed TX/RX chipsets. Therefore, the TX/RX front-end circuitry is mounted in compact split-block waveguide modules in a collaborative teamwork. The D-band TX/RX front-end modules were integrated into radio units demonstrating successfully a real time error-free wireless data transmission with 5.3 Gbit/s using 64 QAM modulation over a 1 GHz channel with spectrum efficiency of 5 bit/s/Hz. The work from this thesis demonstrates the world’s first fully functional spectrum efficient link at frequencies greater than 100 GHz.
high data rate