Zero Loads: Canceling Load Requests by Tracking Zero Values
Paper in proceeding, 2008

The considerable gap between processor and DRAM speed and the power losses in the cache hierarchy calls for more efficient approaches. Broadly speaking, cache-hierarchy efficiency can be increased either by improving cache management or by reducing the number of load instructions that reach the cache hierarchy. We introduce the notion of zero loads to approach the latter. This paper explores the potential of tracking locations that contain the value 'zero'. Loads directed to such locations - termed Zero Loads - can be cancelled before they are issued in the cache hierarchy. We find that as many as 21% of the loads are Zero Loads and about one third of them are critical, i.e., ends up on the critical memory path for out-of-order cores. Motivated by this observation, we explore two innovative structures to capture Zero Loads by essentially book-keeping earlier visited blocks/locations that return 'zero'. These schemes are shown to be capable of improving performance and power/energy efficiency considerably.


Mafijul Islam

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Per Stenström

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

1089795X (ISSN)

Vol. 310 16-23
9781605582436 (ISBN)

Subject Categories

Computer and Information Science





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