EPI SGA2
Research Project, 2022
– 2024
Digital sovereignty has become a key requirement for the EU, which is now striving to move from a simple user of ICT technologies to a main player on the digital market, both for products and human skills. Also, the need for EU (and the EuroHPC JU) to deploy Europe world-class exascale supercomputers is urging. The European Processor Initiative develops a roadmap for future European high-performance low power processors aligned with the EuroHPC roadmap.
EPI focuses on processor technologies based on ARM ISA and architecture for covering the short term needs and HPC accelerator technologies based on RISC-V, the open-source ISA. RISC-V is also candidate to become the Europea's own technologies for covering long term objectives. SGA2 also seeks to expand the scope of the project into adjacent European and global vertical markets that can leverage HPC to enable new and improved systems and solutions.
The present EPI SGA2 proposal, built on top of EPI SGA1 represents the second step toward the implementation of this roadmap. This second step will have a three-year duration with the following objectives:
Finalize the development and the bring-up of the first generation of low-power processor units developed in SGA1,
Develop the second generation of the General Purpose Processor (GPP) applying technological enhancements targeting the European Exascale machines with respect to the GPP (Rhea) of SGA1,
Develop the second generation of low-power accelerator test chips, usable by the HPC community for tests and finally
Develop sound and realistic industrialisation & commercialisation paths and Enable long-term economical sustainability with an industrialization path in the edge computing area, demonstrated in a few well-chosen proofs of concepts like autonomous shuttles or video surveillance.
Participants
Per Stenström (contact)
Chalmers, Computer Science and Engineering (Chalmers), Computer and Network Systems
Miquel Pericas
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Pedro Petersen Moura Trancoso
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Ioannis Sourdis
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Collaborations
BMW
Muenchen, Germany
Barcelona Supercomputing Center (BSC)
Barcelona, Spain
CINECA
Casalecchio di Reno, Italy
Compagnie Des Machines Bull S.A.
Paris, France
E4 Computer Engineering SpA
Scandiano, Italy
Elektrobit Automotive
Erlangen, Germany
Extoll GmbH
Mannheim, Germany
Forschungszentrum Jülich
Juelich, Germany
Foundation for Research and Technology Hellas (FORTH)
Heraklion, Greece
Fraunhofer-Gesellschaft Zur
Munchen, Germany
Genci grand équipement national de calcul intensif (GENCI)
Paris, France
Infineon Technologies
Neubiberg, Germany
Kalray
Montbonnot, France
Karlsruhe Institute of Technology (KIT)
Karlsruhe, Germany
Kernkonzept
Dresden, Germany
Leonardo - Societa per azioni
Roma, Italy
Menta
Valbonne, France
PROVEnRUN
Paris, France
STMicroelectronics Agrate
Agrate Brianza, Italy
SemiDynamics
Barcelona, Spain
SiPearl
Maisons-Laffitte, Metropolitan France
Surfsara Bv
Utrecht, Netherlands
Swiss Federal Institute of Technology in Zürich (ETH)
Zürich, Switzerland
The French Alternative Energies and Atomic Energy Commission (CEA)
Gif-sur-Yvette, France
University of Bologna
Bologna, Italy
University of Lisbon
Lisboa, Portugal
University of Pisa
Pisa, Italy
University of Zagreb, Faculty of Electrical Engineering and Computing
Zagreb, Croatia
ZeroPoint Technologies
Göteborg, Sweden
Funding
European Commission (EC)
Project ID: 101036168
Funding Chalmers participation during 2022–2024
Related Areas of Advance and Infrastructure
Information and Communication Technology
Areas of Advance