Channel noise in two-dimensional field-effect electron devices
Research Project, 2023
We lack detailed knowledge on the physical origin of high-frequency noise in solid-state transistors based on a two-dimensional (2D) sheet of charge carriers. State-of-the-art devices exhibit five times higher noise than the quantum-noise limit and temperature scaling does not reduce transistor noise below 20 K. The channel noise in the field-effect transistor (FET) constitutes the major reason for reduced detection capability in today’s most sensitive microwave receivers. We intend to estimate the channel noise in the InGaAs high-electron mobility transistor used in such receivers. By testing different heterostructures, we control the electron temperature and the amount of thermionic emission between channel and barrier. Channel noise will be measured at several different temperatures down to 4 K. The results will be compared with a recent theory on partition noise in 2D FETs based on real-space transfer as a mechanism responsible for channel noise. We also intend to investigate the subthreshold swing in the 2D FET down to 4 K. We hypothesize that the DC properties of the transistor below voltage threshold is connected to the channel noise as suggested by preliminary measurements. Our final aim is to experimentally demonstrate a noise temperature at twice the quantum noise limit at 6 GHz. This would have a transformative impact om many fundamental studies today limited by high-frequency noise such as detection of qubits, dark matter searches and radio astronomy.
Jan Grahn (contact)
Chalmers, Microtechnology and Nanoscience (MC2), Terahertz and Millimetre Wave Laboratory
Swedish Research Council (VR)
Project ID: 2022-04682
Funding Chalmers participation during 2023–2026