PRIME: Principled Designs of Processing-in-Memory Parallel Systems
Computers have enjoyed a phenomenal progress in performance thanks to a doubling of the transistor count on a die, biannually since 1970s. However, this trend is expected to soon end which calls for radically new principles for computer design. Major challenges are how to continue exponential improvements in computational performance and energy efficiency.PRIME addresses these challenges by departing from von Neumann based to data-centric computational models where computations move to where data resides instead of the opposite as in von Neumann based models. Time is ripe for a paradigm shift to data-centric models because of the emergence of 3D-stacked memory chips that can embed computing in memory and a data centric application trend.PRIME envisions massively parallel systems of Processing-In-Memory nodes that can solve demanding problems. It addresses the challenges of data mapping and task scheduling problems to envision the PIM paradigm. PRIME focuses on large-scale multi-PIM parallel systems. Important issues that will be addressed are strategies for how to map data and schedule tasks to maximize parallelism and minimize data transfers and the design of multi-level memory hierarchies in a parallel PIM-chip system. The scientific relevance is high as breakthroughs in this area are likely to impact industrial uptake with the emergence of memory-chip technologies that can adopt the new methodologies.
Per Stenström (contact)
Full Professor at Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Pedro Petersen Moura Trancoso
Associate Professor at Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers), Computer Systems
Swedish Research Council (VR)
Funding Chalmers participation during 2019–2023