Improvement of AM-PM in a 33-GHz CMOS SOI Power Amplifier Using pMOS Neutralization
Journal article, 2019

This letter presents two highly efficient two-stage power amplifiers (PAs) for 5G applications, implemented in a 22-nm slilicon on insulator (SOI) CMOS technology. High efficiency is achieved by carefully designing the power cells and optimizing the layout. Capacitive neutralization is used to improve the stability and the gain. Both PAs are similar except for the use of nMOS neutralization capacitors in the first one. In the second PA, we propose the use of pMOS capacitors instead to enhance significantly both stability and AM-PM linearity at the same time. For both PAs, the saturated output power is 12.7 dBm andP1 dB is 11.9 dBm from a 0.9-V supply at 33 GHz with a power-added efficiency (PAE) at P1 dB of more than 36%. The PAE at Psat is 38% and 40% for the PA with nMOS and pMOS neutralizations, respectively. The AM-PM up to P3 dB for the PA with nMOS neutralization is 7, and for the one with pMOS neutralization, it is less than 1.3 thanks to the proposed technique.

CMOS technology

5G

efficient

AM-AM

power amplifier (PA)

power-added efficiency (PAE)

linearity

AM-PM linearization

Author

Mohammed Abdulaziz

Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics, Microwave Electronics

Ericsson

Halil Volkan Hünerli

Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics

Koen Buisman

Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics

Christian Fager

Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics, Microwave Electronics

IEEE Microwave and Wireless Components Letters

1531-1309 (ISSN)

Vol. 29 12 798-801

Subject Categories

Telecommunications

Signal Processing

Other Electrical Engineering, Electronic Engineering, Information Engineering

DOI

10.1109/LMWC.2019.2948763

More information

Latest update

2/7/2020 9