LV*: A Low Complexity Lazy Versioning HTM Infrastructure
Paper in proceeding, 2010
Parallel architectures
Hardware transactional memory
Author
Anurag Negi
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Mridha Mohammad Waliullah
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Per Stenström
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Proceedings - 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2010
231-240
978-142447938-2 (ISBN)
Subject Categories
Computer and Information Science
DOI
10.1109/ICSAMOS.2010.5642062
ISBN
978-142447938-2