Power Gating Multiplier of Embedded Processor Datapath
Paper in proceedings, 2011

Leakage power is an important concern in modern electronic designs. To efficiently employ power gating for leakage reduction in embedded processors, the architecture must provide a clear-cut software support for power gating and the power-gated unit must have significant idle times during the execution of the applications. We introduce power gating of individual datapath units for the embedded architecture of FlexCore, to evaluate if leakage reductions in temporarily idle units can reduce the overall power dissipation of compute-intensive applications. Post-layout multi-corner simulations for a 65-nm FlexCore datapath implementation demonstrate that power gating of the multiplier unit yields overall datapath energy savings, up to 14%, for two EEMBC benchmarks.

Author

Tung Hoang

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Vineeth Saseendran

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Donatas Siaudinis

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Per Larsson-Edefors

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Proceedings of 7th Conference on Ph.D Research in Microelectronics and Electronics (PRIME) Madonna di Campiglio, Trento; 3 July 2011 through 7 July 2011

41-44

Areas of Advance

Information and Communication Technology

Subject Categories

Other Electrical Engineering, Electronic Engineering, Information Engineering

DOI

10.1109/PRIME.2011.5966212

ISBN

978-1-4244-9136-0

More information

Created

10/7/2017