Per Larsson-Edefors

Professor at Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Projects

2014–2019

Energy-efficient optical fibre communication

Erik Agrell Communication Systems
Christoffer Fougstedt Computer Engineering (Chalmers)
Anders Larsson Photonics
Peter Andrekson Photonics
Alexandre Graell i Amat Communication Systems
Kevin Cushon Computer Engineering (Chalmers)
Alireza Sheikh Communication Systems
Per Larsson-Edefors Computer Engineering (Chalmers)
Magnus Karlsson Photonics
Lars Lundberg Photonics
Knut and Alice Wallenberg Foundation

There might be more projects where Per Larsson-Edefors participates, but you have to be logged in as a Chalmers employee to see them.

Publications

2017

Improved Low-Power LDPC FEC for Coherent Optical Systems

Kevin Cushon, Peter Andrekson, Per Larsson-Edefors
Paper in proceedings
2017

CREEP: Chalmers RTL-based Energy Evaluation of Pipelines

Daniel Moreau, Alen Bardizbanyan, Magnus Själander et al
Report
2017

Data filter cache designs for enhancing energy efficiency and performance in computing systems

David Whalley, Magnus Själander, Alen Bardizbanyan et al
Patent
2017

Instruction level energy model for the Adapteva Epiphany multi-core processor

Gabriel Ortiz, Lars Svensson, Erik Alveflo et al
14th ACM International Conference on Computing Frontiers, CF 2017, Siena, Italy, 15-17 May 2017, p. 380-384
Paper in proceedings
2017

Low-Power Low-Latency BCH Decoders for Energy-Efficient Optical Interconnects

Christoffer Fougstedt, Krzysztof Szczerba, Per Larsson-Edefors
Journal of Lightwave Technology. Vol. PP (99)
Journal article
2017

A 3-GHz Reconfigurable 2/3-Level 96/48-Channel Cross-Correlator for Synthetic Aperture Radiometry

Erik J Ryman, Anders Emrich, Lars Svensson et al
Paper in proceedings
2017

Time-Domain Digital Back Propagation: Algorithm and Finite-Precision Implementation Aspects

Christoffer Fougstedt, Mikael Mazur, Lars Svensson et al
Optical Fiber Communications Conference and Exhibition, p. Article no 7937325-
Paper in proceedings
2017

Systems and methods for improving processor efficiency through caching

David Whalley, Magnus Själander, Alen Bardizbanyan et al
Patent
2017

Finite-Precision Optimization of Time-Domain Digital Back Propagation by Inter-Symbol Interference Minimization

Christoffer Fougstedt, Lars Svensson, Mikael Mazur et al
Paper in proceedings
2016

Logic Filter Cache for Wide-VDD-Range Processors

Alen Bardizbanyan, Oskar Andersson, Joachim Rodrigues et al
Proceedings of 23rd IEEE Int. Conf. on Electronics, Circuits and Systems, p. 376-379
Paper in proceedings
2016

Low-Power 400-Gbps Soft-Decision LDPC FEC for Optical Transport Networks

Kevin Cushon, Per Larsson-Edefors, Peter Andrekson
Journal of Lightwave Technology. Vol. 34 (18), p. 4304-4311
Journal article
2016

Practical Way Halting by Speculatively Accessing Halt Tags

Daniel Moreau, Alen Bardizbanyan, Magnus Själander et al
19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016, Dresden, Germany, 14-18 March 2016, p. 1375-1380
Paper in proceedings
2016

Power Consumption of a Minimal-DSP Coherent Link with a Polarization Multiplexed Pilot-Tone

Lars Lundberg, Christoffer Fougstedt, Per Larsson-Edefors et al
Paper in proceedings
2016

Dispersion Compensation FIR Filter with Improved Robustness to Coefficient Quantization Errors

Alireza Sheikh, Christoffer Fougstedt, Alexandre Graell i Amat et al
Journal of Lightwave Technology. Vol. 34 (22), p. 5110-5117
Journal article
2016

Dynamic Equalizer Power Dissipation Optimization

Christoffer Fougstedt, Pontus Johannisson, Lars Svensson et al
Paper in proceedings
2016

Redesigning a tagless access buffer to require minimal ISA changes

Carlos Sanchez, Peter Gavin, Daniel Moreau et al
Proceedings of the IEEE/ACM International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, p. Article number 2968504-
Paper in proceedings
2015

Dispersion Compensation Filter Design Optimized for Robustness and Power Efficiency

Alireza Sheikh, Christoffer Fougstedt, Alexandre Graell i Amat et al
Signal Processing in Photonics Communications, SPPCom 2015; Boston, MA; United States; 27 June 2015 through 1 July 2015, p. SpT3D.2-
Paper in proceedings
2015

Impact of Forward Error Correction on Energy Consumption of VCSEL-based Transmitters

Krzysztof Szczerba, Christoffer Fougstedt, Per Larsson-Edefors et al
Paper in proceedings
2015

Exploring early and late ALUs for single-issue in-order pipelines

Alen Bardizbanyan, Per Larsson-Edefors
Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015. New York City, United States, 18-21 October 2015, p. 543-548
Paper in proceedings
2015

Improving Data Access Efficiency by Using Context-Aware Loads and Stores

Alen Bardizbanyan, Magnus Själander, David Whalley et al
SIGPLAN Notices (ACM Special Interest Group on Programming Languages). Vol. 50 (5), p. 27-36
Paper in proceedings
2015

Energy-Efficient Soft-Decision LDPC FEC for Long-Haul Optical Communication

Kevin Cushon, Per Larsson-Edefors, Peter Andrekson
Paper in proceedings
2015

Power-Efficient Time-Domain Dispersion Compensation Using Optimized FIR Filter Implementation

Christoffer Fougstedt, Alireza Sheikh, Pontus Johannisson et al
Signal Processing in Photonics Communications, SPPCom 2015; Boston, MA; United States; 27 June 2015-1 July 2015, p. SpT3D.3-
Paper in proceedings
2014

Reducing set-associative L1 data cache energy by early load data dependence detection (ELD3)

Alen Bardizbanyan, M. Själander, D.B. Whalley et al
Proceedings -Design, Automation and Test in Europe, DATE
Paper in proceedings
2014

Evaluating Branch Predictor Configurations for a MIPS-like Pipeline

Fredrik Brosser, Karthik Manchanahalli Rajendra Prasad, Alen Bardizbanyan et al
Conference contribution
2014

Timing- and power-driven ALU design training using spreadsheet-based arithmetic exploration

Per Larsson-Edefors, Kjell Jeppson
10th European Workshop on Microelectronics Education, EWME 2014, p. 151-154
Paper in proceedings
2014

1.6 GHz Low-Power Cross-Correlator System Enabling Geostationary Earth Orbit Aperture Synthesis

Erik J Ryman, A. Emrich, Stefan Andersson et al
IEEE Journal of Solid-State Circuits. Vol. 49 (11), p. 2720-2729
Journal article
2014

Assessing Scrubbing Techniques for Xilinx SRAM-based FPGAs in Space Applications

Fredrik Brosser, Emil Milh, Vilhelm Geijer et al
Proceedings of the 2014 International Conference on Field-Programmable Technology, p. 296-299
Paper in proceedings
2014

MIDAS: Model for IP-inclusive DFM assessment of system manufacturability

KASYAB PARMESH SUBRAMANIYAN, Per Larsson-Edefors
5th European Workshop on CMOS Variability, VARI 2014. Palma de Mallorca, SPAIN, SEP 29-OCT 01, 2014, p. Art. no. 6957079-
Paper in proceedings
2013

A SiGe 8-Channel Comparator for Application in a Synthetic Aperture Radiometer

Erik J Ryman, Stefan Andersson, Johan Riesbeck et al
Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, May 19-23 2013, p. 845-848
Paper in proceedings
2013

Improving Data Access Efficiency by Using a Tagless Access Buffer (TAB)

Alen Bardizbanyan, Peter Gavin, David Whalley et al
Proceedings of the International Symposium on Code Generation and Optimization (CGO), Shenzhen, China, Feb. 23-27, p. 269-279
Paper in proceedings
2013

Designing a Practical Data Filter Cache to Improve Both Energy Efficiency and Performance

Alen Bardizbanyan, Magnus Själander, David Whalley et al
Transactions on Architecture and Code Optimization. Vol. 10 (4), p. 25 pages-
Journal article
2013

Exploring prefix-tree adders using excel spreadsheets

Kjell Jeppson, Per Larsson-Edefors
2013 9th IEEE International Conference on Microelectronic Systems Education, MSE 2013. Vol. Austin, Texas 2-3 June 2013, p. 48-51
Paper in proceedings
2013

Towards a Performance- and Energy-Efficient Data Filter Cache

Alen Bardizbanyan, Magnus Själander, David Whalley et al
Workshop on Optimizations for DSP and Embedded Systems (ODES), Proceedings of International Symposium on Code Generation and Optimization (CGO), Shenzhen, China, Feb. 23-27,, p. 21-28
Paper in proceedings
2013

Development of a Cross-Correlator System for Space-Borne Earth Observation Interferometric Imaging

Erik J Ryman, Anders Emrich, Stefan Back Andersson et al
Paper in proceedings
2013

FlexCore: Implementing an Exposed Datapath Processor

Magnus Själander, Per Larsson-Edefors
Proceedings of International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, Samos, Greece, July 15-18, p. 306-313
Paper in proceedings
2013

Manufacturable Nanometer Designs using Standard Cells with Regular Layout

KASYAB PARMESH SUBRAMANIYAN, Per Larsson-Edefors
Proceedings of International Symposium on Quality Electronic Design (ISQED), Santa Clara, USA, March 4-6, 2013, p. 398-405
Paper in proceedings
2013

Speculative Tag Access for Reduced Energy Dissipation in Set-Associative L1 Data Caches

Alen Bardizbanyan, Magnus Själander, David Whalley et al
Proceedings of IEEE International Conference on Computer Design (ICCD), Asheville, NC, USA, October 6-9 2013, p. 302-308
Paper in proceedings
2013

Methodology for Power-Aware Coherent Receiver Design

Tauseef Ahmad, Yun Ai, Pavithra Muralidharan et al
Advanced Photonics Congress (SPPCom) 2013, p. SPT4D.4-
Paper in proceedings
2012

Viterbi Accelerator for Embedded Processor Datapaths

Muhammad Waqar Azhar, Magnus Själander, Ali Hasan et al
2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2012, Delft, 9 - 11 July 2012, p. 133-140
Paper in proceedings
2012

Training Design Methodology Skills at the Master’s Level

Per Larsson-Edefors, Kjell Jeppson
European Workshop on Microelectronics Education. Vol. 2012 (9-11 May, 2012), p. 10-13
Paper in proceedings
2012

Configurable RTL Model for Level-1 Caches

Vahid Saljooghi, Alen Bardizbanyan, Magnus Själander et al
Paper in proceedings
2012

Feasibility Study of FPGA-Based Equalizer for 112-Gbit/s Optical Fiber Receivers

Fredrik Toft, Niclas Rousk, Jonas Mårtensson et al
IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, 20-23 May 2012, p. 3234-3237
Paper in proceedings
2012

Application of an Eight-Channel Comparator in a Cross-Correlator for Synthetic Aperture Radiometry

Erik J Ryman, Anders Emrich, Stefan Andersson et al
Paper in proceedings
2012

Data-Width-Driven Power Gating of Integer Arithmetic Circuits

Tung Hoang, Per Larsson-Edefors
Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Amherst, 19-21 August 2012 (Article number 6296479), p. 237-242
Paper in proceedings
2012

On Regularity and Integrated DFM Metrics

KASYAB PARMESH SUBRAMANIYAN, Per Larsson-Edefors
4th Asia Symposium on Quality Electronic Design (ASQED), Malaysia, July 10-11, 2012, p. 211-218
Paper in proceedings
2011

Application-Specific Energy Optimization of General-Purpose Datapath Interconnect

Babak Hidaji, Salar Alipour, KASYAB PARMESH SUBRAMANIYAN et al
Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), p. 301-306
Paper in proceedings
2011

A SAT-Based Compiler for FlexCore

Nikita Frolov, Magnus Själander, Per Larsson-Edefors et al
Report
2011

Declarative, SAT-solver-based Scheduling for an Embedded Architecture with a Flexible Datapath

Nikita Frolov, Magnus Själander, Per Larsson-Edefors et al
Conference contribution
2011

Reconfigurable Instruction Decoding for a Wide-Control-Word Processor

Alen Bardizbanyan, Magnus Själander, Per Larsson-Edefors
Proceedings of Reconfigurable Architectures Workshop (RAW), IEEE International Parallel & Distributed Processing Symposium (IPDPS), p. 322-325
Paper in proceedings
2011

Extracting Vectors from Application Traces for Power Integrity Analysis

Martin Olsson, Johnny Pihl, Daniel Andersson et al
Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI). Naples, 8-11 May 2011, p. 39-42
Paper in proceedings
2011

FlexDEF: Development Framework for Processor Architecture Implementation and Evaluation

KASYAB PARMESH SUBRAMANIYAN, Erik J Ryman, Magnus Själander et al
Proceedings of 7th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), p. 37-40
Paper in proceedings
2011

3.6-GHz 0.2-mW/ch/GHz 65-nm Cross-Correlator for Synthetic Aperture Radiometry

Erik J Ryman, Anders Emrich, Stefan Andersson et al
Proceedings of the 33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011, San Jose, 19-21 September 2011
Paper in proceedings
2011

Power Gating Multiplier of Embedded Processor Datapath

Tung Hoang, Vineeth Saseendran, Donatas Siaudinis et al
Proceedings of 7th Conference on Ph.D Research in Microelectronics and Electronics (PRIME) Madonna di Campiglio, Trento; 3 July 2011 through 7 July 2011, p. 41-44
Paper in proceedings
2010

Implementing Constructive Alignment in a CDIO-oriented Master’s Program in Integrated Electronic System Design

Kjell Jeppson, Lena Peterson, Lars Svensson et al
Proceedings of European Workshop on Microelectronics Education, p. 135-140
Paper in proceedings
2010

Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor

Muhammad Waqar Azhar, Tung Hoang, Per Larsson-Edefors
Proceedings of Euromicro Conference on Digital System Design (DSD), p. 675-680
Paper in proceedings
2010

On-chip Power Supply Noise and Its Implications on Timing

Lars Svensson, Johnny Pihl, Daniel Andersson et al
Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), p. 389-392
Paper in proceedings
2010

A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit

Tung Hoang, Magnus Själander, Per Larsson-Edefors
IEEE Transactions on Circuits and Systems I: Regular Papers. Vol. 57 (12), p. 3073-3081
Journal article
2010

Datapath Interconnect Optimization Engine for Energy-Efficient FlexCore Configurations

Babak Hidaji, Salar Alipour, Jacob Lidman et al
Conference contribution
2010

Design Space Exploration for an Embedded Processor with Flexible Datapath Interconnect

Tung Hoang, Ulf Jälmbrant, Erik der Hagopian et al
Proceedings of IEEE Int. Conf. on Application-specific Systems, Architectures and Processors (ASAP), p. 55-62
Paper in proceedings
2010

A Single-Chip 64 Input Low Power High Speed Cross-Correlator for Space Application

Erik J Ryman, Per Larsson-Edefors, Lars Svensson et al
Paper in proceedings
2010

FlexTools: Design Space Exploration Tool Chain from C to Physical Implementation

Erik J Ryman, KASYAB PARMESH SUBRAMANIYAN, Tung Hoang et al
Paper in proceedings
2010

FlexTools: Design Space Exploration Tool Chain from C to Physical Implementation

Erik J Ryman, KASYAB PARMESH SUBRAMANIYAN, Tung Hoang et al
Paper in proceedings
2010

Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor

Muhammad Waqar Azhar, Tung Hoang, Per Larsson-Edefors
Proceedings of Euromicro Conference on Digital System Design (DSD), p. 675-680
Paper in proceedings
2010

Teaching Bachelors Electronic Circuits with Electronic Systems Design in Mind

Per Larsson-Edefors
International Journal of Electrical Engineering Education. Vol. 47 (3), p. 263-276
Journal article
2010

Generation and Exploration of Layouts for Area-Efficient Barrel Shifters

Alen Bardizbanyan, KASYAB PARMESH SUBRAMANIYAN, Per Larsson-Edefors
Proceedings of IEEE Computer Society Annual Symp. on VLSI (ISVLSI), p. 454-455
Paper in proceedings
2010

Accelerating Cyclic Redundancy Checking (CRC) Computation in the FlexCore Processor

Muhammad Waqas, Tung Hoang, Per Larsson-Edefors
Conference contribution
2010

Digital Cross-Correlators: Two Approaches

Erik J Ryman, A. Emrich, J. Embretsen et al
Paper in proceedings
2010

Impact of Standard Cell Pin Placement on Routing Regularity of HPM Architectures

Affaq Qamar, KASYAB PARMESH SUBRAMANIYAN, Per Larsson-Edefors
Conference contribution
2009

Fast Layout Exploration Using the Wired System

Emil Axelsson, KASYAB PARMESH SUBRAMANIYAN, Mary Sheeran et al
Conference contribution
2009

High-Performance 64-input Cross-Correlator

Erik J Ryman, Per Larsson-Edefors, Anders Emrich et al
Conference contribution
2009

3D chip stacking using planarized carbon nanotubes as through-silicon-vias

Kjell Jeppson, Teng Wang, Johan Liu et al
Conference contribution
2009

Double Throughput Multiply-Accumulate Unit for FlexCore Processor Enhancements

Tung Hoang, Magnus Själander, Per Larsson-Edefors
Paper in proceedings
2009

Layout Exploration of Geometrically Accurate Arithmetic Circuits

KASYAB PARMESH SUBRAMANIYAN, Emil Axelsson, Mary Sheeran et al
Paper in proceedings
2009

Scheduling for an Embedded Architecture with a Flexible Datapath

Thomas Schilling, Magnus Själander, Per Larsson-Edefors
Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), p. 151-156
Paper in proceedings
2009

Layout Exploration of Geometrically Accurate Arithmetic Circuits

KASYAB PARMESH SUBRAMANIYAN, Emil Axelsson, Mary Sheeran et al
Paper in proceedings
2009

Towards Supply-Grid-Based Derating of Timing Margins

Lars Svensson, Johnny Pihl, Daniel Andersson et al
Paper in proceedings
2009

Custom Layout Strategy for Rectangle-Shaped Log-Depth Multiplier Reduction Tree

Patrik Kimfors, Niklas Broman, Andreas Haraldsson et al
Paper in proceedings
2009

FlexCore: Utilizing Exposed Datapath Control for Efficient Computing

Martin Thuresson, Magnus Själander, Magnus Björk et al
Journal of Signal Processing Systems. Vol. 57 (1), p. 5-19
Journal article
2009

Ultra-Low-Power 2-Cycle Multiply-Accumulate Architecture

Tung Hoang, Magnus Själander, Per Larsson-Edefors
Conference contribution
2009

Supply Voltage Drop Study Considering On-Chip Self Inductance of a 32-bit Processor's Power Grid

Daniel Andersson, Björn Nilsson, Johnny Pihl et al
Paper in proceedings
2009

High-Speed, Energy-Efficient 2-Cycle Multiply-Accumulate Architecture

Tung Hoang, Magnus Själander, Per Larsson-Edefors
Proceedings of IEEE Intl SoC Conference (SoCC), p. 119-122
Paper in proceedings
2009

Multiplication Acceleration through Twin Precision

Magnus Själander, Per Larsson-Edefors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Vol. 17 (9), p. 1233-1246
Journal article
2009

Design-Time Scheduling for Processor Exploration

Ulf Jälmbrant, Erik der Hagopian, Magnus Själander et al
Conference contribution
2008

High-Speed and Low-Power Multipliers Using the Baugh-Wooley Algorithm and HPM Reduction Tree

Magnus Själander, Per Larsson-Edefors
15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008; St. Julian's; Malta; 31 August 2008 through 3 September 2008, p. 33-36
Paper in proceedings
2008

Double Throughput MAC for Performance Enhancement of the FlexCore Processor

Tung Hoang, Magnus Själander, Per Larsson-Edefors
Conference contribution
2008

Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach

Daniel Andersson, Lars Svensson, Per Larsson-Edefors
Proceedings of Intl Symp. on Quality Electronic Design (ISQED), p. 663-669
Paper in proceedings
2008

Time-Domain Interconnect Characterisation Flow for Appropriate Model Segmentation

Daniel Andersson, Lars Svensson, Per Larsson-Edefors
IET Computers & Digital Techniques. Vol. 2 (4), p. 265-274
Journal article
2008

The Case for HPM-Based Baugh-Wooley Multipliers

Magnus Själander, Per Larsson-Edefors
Report
2008

Noise Interaction Between Power Distribution Grids and Substrate

Daniel Andersson, Simon Kristiansson, Lars Svensson et al
Proceedings of Intl Symp. on Quality Electronic Design (ISQED), p. 84-90
Paper in proceedings
2008

A New Master's Program in Integrated Electronic System Design

Kjell Jeppson, Lena Peterson, Lars Svensson et al
European Workshop on Microelectronics Education. Vol. EWME 2008 (Budapest)
Paper in proceedings
2007

FlexCore: Utilizing Exposed Datapath Control for Efficient Computing

Martin Thuresson, Magnus Själander, Magnus Björk et al
IEEE SAMOS 2007, p. 18-25
Paper in proceedings
2007

Overdrive Power-Gating Techniques for Total Power Minimization

Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Svensson
Paper in proceedings
2007

A Flexible Datapath Interconnect for Embedded Applications

Magnus Själander, Per Larsson-Edefors, Magnus Björk
IEEE Computer Society Annual Symposium on VLSI, p. 15-20
Paper in proceedings
2007

Current Probing Methodology for Static Power Extraction in Sub-90nm CMOS Circuits

Minh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis
Report
2007

Exposed Datapath for Efficient Computing

Magnus Björk, Magnus Själander, Lars Svensson et al
Paper in proceedings
2007

Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays

Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors et al
8th International Symposium on Quality Electronic Design (ISQED’07), p. 185 - 191
Paper in proceedings
2007

High-Accuracy Architecture-Level Power Estimation for Partitioned Arrays in a 65-nm CMOS BPTM Process

Minh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis
Paper in proceedings
2007

Toward a Systematic Sensitivity Analysis of On-Chip Power Grids Using Factor Analysis

Daniel Andersson, Lars Svensson, Per Larsson-Edefors
Paper in proceedings
2006

Multiplier Reduction Tree with Logarithmic Logic Depth and Regular Connectivity

Henrik Eriksson, Per Larsson-Edefors, Mary Sheeran et al
Paper in proceedings
2006

Toward Architecture-Based Test-Vector Generation for Timing Verification of Fast Parallel Multipliers

Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert
Journal article
2006

Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration

Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors et al
Paper in proceedings
2006

Architecture-Level Power Estimation and Scaling Trends for SRAM Arrays

Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors
Conference contribution
2006

Exposed Datapath for Efficient Computing

Magnus Björk, Magnus Själander, Lars Svensson et al
Report
2006

Multiplier Reduction Tree with Logarithmic Logic Depth and Regular Connectivity

Henrik Eriksson, Per Larsson-Edefors, Mary Sheeran et al
Paper in proceedings
2006

Interconnect Characterization Flow for Minimal-Segment Model Selection

Daniel Andersson, Lars Svensson, Per Larsson-Edefors
Paper in proceedings
2006

An Efficient FFT Engine Based on Twin-Precision Computation

Martin Brinck, Kristian Eklund, Magnus Själander et al
Conference contribution
2005

A Power-Efficient and Versatile Modified-Booth Multiplier

Magnus Själander, Per Larsson-Edefors
Conference contribution
2005

Fast Dual-Rail Dynamic Logic Style

A Alvandpour, Per Larsson-Edefors, R Krishnamurthy et al
Patent
2005

Accounting for the Skin Effect during Repeater Insertion

Daniel Andersson, Lars Svensson, Per Larsson-Edefors
2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05; Chicago, IL; United States; 17 April 2005 through 19 April 2005, p. 32-37
Paper in proceedings
2005

A Low-Leakage Twin-Precision Multiplier Using Reconfigurable Power Gating

Magnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors et al
IEEE International Symposium on Circuits and Systems, p. 1654-7
Paper in proceedings
2004

A Power Cut-Off Technique for Gate Leakage Suppression

Mindaugas Drazdziulis, Per Larsson-Edefors, Daniel Eckerbert et al
European Solid-State Circuits Conference (ESSCIRC), p. 171-174
Paper in proceedings
2004

Table-Based Total Power Consumption Estimation of Memory Arrays for Architects

Minh Quang Do, Per Larsson-Edefors, Lars Bengtsson
Lecture Notes in Computer Science (LNCS) , Springer Verlag. Vol. 3254 (1), p. 869-878
Paper in proceedings
2004

Evaluation of Power Cut-Off Techniques in the Presence of Gate Leakage

Mindaugas Drazdziulis, Per Larsson-Edefors
2004 IEEE International Symposium on Cirquits and Systems - Proceedings; Vancouver, BC; Canada; 23 May 2004 through 26 May 2004, p. II745-II748
Paper in proceedings
2004

On Skin Effect in On-Chip Interconnects

Daniel Andersson, Lars Svensson, Per Larsson-Edefors
Intl Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), p. 463-470
Paper in proceedings
2004

An Efficient Twin-Precision Multiplier

Magnus Själander, Henrik Eriksson, Per Larsson-Edefors
International Conference on Computer Design (ICCD), p. 30-33
Paper in proceedings
2004

On Maximum Current Estimation in CMOS Digital Circuits

Dainius Ciuplys, Per Larsson-Edefors
International Conference on VLSI Design, Mumbai, INDIA. JAN 05-09, 2004, p. 658-661
Paper in proceedings
2004

Flash [II] - Domino: A Fast Dual-Rail Dynamic Logic Style

A Alvandpour, Per Larsson-Edefors, R Krishnamurthy et al
Patent
2004

Table Based Total Power Consumption Estimation Approach for Architects

Minh Quang Do, Per Larsson-Edefors, Lars Bengtsson
Conference contribution
2004

Glitch-Conscious Low-Power Design of Arithmetic Circuits

Henrik Eriksson, Per Larsson-Edefors
2004 IEEE International Symposium on Cirquits and Systems - Proceedings; Vancouver, BC; Canada; 23 May 2004 through 26 May 2004. Vol. 2, p. II281-II284
Paper in proceedings
2004

An Efficient Twin-Precision Multiplier

Magnus Själander, Henrik Eriksson, Per Larsson-Edefors
International Conference on Computer Design (ICCD), p. 30-33
Paper in proceedings
2004

A Comparison of Power Cut-Off Techniques Employed for Ripple Carry Adders in the Presence of Gate Leakage

Mindaugas Drazdziulis, Per Larsson-Edefors
Conference contribution
2004

Dynamic Pass-Transistor Dot Operators for Efficient Parallel-Prefix Adders

Henrik Eriksson, Per Larsson-Edefors
International Symposium on Circuits and Systems (ISCAS), Vancouver, CANADA. MAY 23-26, 2004. Vol. 2, p. 461-464
Paper in proceedings
2004

Frequency-Dependent Effects in RLC Interconnects

Daniel Andersson, Lars Svensson, Per Larsson-Edefors
Conference contribution
2003

FlexSoC: Combining Flexibility and Efficiency in SoC Designs

John Hughes, Kjell Jeppson, Per Larsson-Edefors et al
Proceedings of 21st Norchip Conference. Vol. Riga, Latvia, p. 52-55
Paper in proceedings
2003

A Mixed-Mode Delay-Locked Loop Architecture

Daniel Eckerbert, Lars Svensson, Per Larsson-Edefors
Proceedings of the 21st International Conference on Computer Design (ICCD), San Jose, 13-15 October 2003, p. 261-263
Paper in proceedings
2003

A Deep Submicron Power Estimation Methodology Adaptable to Variations Between Power Characterization and Estimation

Daniel Eckerbert, Per Larsson-Edefors
Proceedings of Asia South-Pacific Design Automation Conference (ASPDAC), Kitakyushu, 21-24 January 2003, p. 716-719
Paper in proceedings
2003

Models for Power Consumption Estimation in the DSP-PP Simulator

Minh Quang Do, Lars Bengtsson, Per Larsson-Edefors
Conference contribution
2003

A Gate Leakage Reduction Strategy for Future CMOS Circuits

Mindaugas Drazdziulis, Per Larsson-Edefors
Proceedings of the 29th European Solid-State Circuits Conference, ESSCIRC 2003, Estoril, 16-18 September 2003, p. 317-320
Paper in proceedings
2003

Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects

Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson et al
Paper in proceedings
2003

Characterizing Ripple-Carry Circuits Using Logical Effort

Henrik Eriksson, Per Larsson-Edefors
Conference contribution
2003

On Maximum Current Estimation in CMOS Digital Circuits

Dainius Ciuplys, Per Larsson-Edefors
Conference contribution
2003

Full-Custom vs. Standard-Cell Design Flow - An Adder Case Study

Henrik Eriksson, Henrik Eriksson, Per Larsson-Edefors et al
Proceedings of Asia South-Pacific Design Automation Conference (ASPDAC), Kitakyushu, 21-24 January 2003, p. 507-510
Paper in proceedings
2003

An Investigation of Gate Leakage for Future CMOS Circuits

Mindaugas Drazdziulis, Per Larsson-Edefors
Conference contribution
2003

DSP-PP: A Simulator/Estimator of Power consumption and Performance for Parallel DSP Architectures

Minh Quang Do, Lars Bengtsson, Per Larsson-Edefors
Proceedings of the PDCN'03 Symposium (Parallel and Distributed Computing and Networks), Innsbruck, Austria, Feb 10-13, 2002, pp. 767-772, p. 767-772
Paper in proceedings
2002

Full-Custom vs. Standard-Cell Based Design – An Adder Comparison

Henrik Eriksson, Henrik Eriksson, Per Larsson-Edefors
Conference contribution